[llvm] r200503 - DAGCombine should not produce ISD::OR nodes after operation legalization if they're not legal.

[David Blaikie]

On Thu, Jan 30, 2014 at 4:51 PM, Owen Anderson <resistor at mac.com> wrote:

> Author: resistor
> Date: Thu Jan 30 18:51:43 2014
> New Revision: 200503
>
> URL: http://llvm.org/viewvc/llvm-project?rev=200503&view=rev
> Log:
> DAGCombine should not produce ISD::OR nodes after operation legalization
> if they're not legal.
>

Is this not testable for some reason?


>
> Modified:
>     llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=200503&r1=200502&r2=200503&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 30
> 18:51:43 2014
> @@ -1544,8 +1544,10 @@ SDValue DAGCombiner::visitADD(SDNode *N)
>
>        // If all possibly-set bits on the LHS are clear on the RHS, return
> an OR.
>        // If all possibly-set bits on the RHS are clear on the LHS, return
> an OR.
> -      if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) ==
> ~RHSZero)
> -        return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
> +      if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) ==
> ~RHSZero){
> +        if (!LegalOperations || TLI.isOperationLegal(ISD::OR, VT))
> +          return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
> +      }
>      }
>    }
>
>
>
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