[llvm] r200451 - ARM IAS: support .object_arch
Saleem Abdulrasool
compnerd at compnerd.org
Wed Jan 29 20:46:41 PST 2014
Author: compnerd
Date: Wed Jan 29 22:46:41 2014
New Revision: 200451
URL: http://llvm.org/viewvc/llvm-project?rev=200451&view=rev
Log:
ARM IAS: support .object_arch
The .object_arch directive indicates an alternative architecture to be specified
in the object file. The directive does *not* effect the enabled feature bits
for the object file generation. This is particularly useful when the code
performs runtime detection and would like to indicate a lower architecture as
the requirements than the actual instructions used.
Added:
llvm/trunk/test/MC/ARM/directive-object_arch-2.s
llvm/trunk/test/MC/ARM/directive-object_arch-3.s
llvm/trunk/test/MC/ARM/directive-object_arch-diagnostics.s
llvm/trunk/test/MC/ARM/directive-object_arch.s
Modified:
llvm/trunk/include/llvm/MC/MCStreamer.h
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
Modified: llvm/trunk/include/llvm/MC/MCStreamer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=200451&r1=200450&r2=200451&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCStreamer.h (original)
+++ llvm/trunk/include/llvm/MC/MCStreamer.h Wed Jan 29 22:46:41 2014
@@ -107,6 +107,7 @@ public:
StringRef StringValue = "") = 0;
virtual void emitFPU(unsigned FPU) = 0;
virtual void emitArch(unsigned Arch) = 0;
+ virtual void emitObjectArch(unsigned Arch) = 0;
virtual void finishAttributeSection() = 0;
virtual void emitInst(uint32_t Inst, char Suffix = '\0') = 0;
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=200451&r1=200450&r2=200451&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Jan 29 22:46:41 2014
@@ -298,6 +298,7 @@ class ARMAsmParser : public MCTargetAsmP
bool parseDirectiveUnwindRaw(SMLoc L);
bool parseDirectiveTLSDescSeq(SMLoc L);
bool parseDirectiveMovSP(SMLoc L);
+ bool parseDirectiveObjectArch(SMLoc L);
StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
bool &CarrySetting, unsigned &ProcessorIMod,
@@ -8090,6 +8091,8 @@ bool ARMAsmParser::ParseDirective(AsmTok
return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
else if (IDVal == ".movsp")
return parseDirectiveMovSP(DirectiveID.getLoc());
+ else if (IDVal == ".object_arch")
+ return parseDirectiveObjectArch(DirectiveID.getLoc());
return true;
}
@@ -9093,6 +9096,45 @@ bool ARMAsmParser::parseDirectiveMovSP(S
return false;
}
+
+/// parseDirectiveObjectArch
+/// ::= .object_arch name
+bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
+ if (getLexer().isNot(AsmToken::Identifier)) {
+ Error(getLexer().getLoc(), "unexpected token");
+ Parser.eatToEndOfStatement();
+ return false;
+ }
+
+ StringRef Arch = Parser.getTok().getString();
+ SMLoc ArchLoc = Parser.getTok().getLoc();
+ getLexer().Lex();
+
+ unsigned ID = StringSwitch<unsigned>(Arch)
+#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
+ .Case(NAME, ARM::ID)
+#define ARM_ARCH_ALIAS(NAME, ID) \
+ .Case(NAME, ARM::ID)
+#include "MCTargetDesc/ARMArchName.def"
+#undef ARM_ARCH_NAME
+#undef ARM_ARCH_ALIAS
+ .Default(ARM::INVALID_ARCH);
+
+ if (ID == ARM::INVALID_ARCH) {
+ Error(ArchLoc, "unknown architecture '" + Arch + "'");
+ Parser.eatToEndOfStatement();
+ return false;
+ }
+
+ getTargetStreamer().emitObjectArch(ID);
+
+ if (getLexer().isNot(AsmToken::EndOfStatement)) {
+ Error(getLexer().getLoc(), "unexpected token");
+ Parser.eatToEndOfStatement();
+ }
+
+ return false;
+}
/// Force static initialization.
extern "C" void LLVMInitializeARMAsmParser() {
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp?rev=200451&r1=200450&r2=200451&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp Wed Jan 29 22:46:41 2014
@@ -136,6 +136,7 @@ class ARMTargetAsmStreamer : public ARMT
virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
StringRef StrinValue);
virtual void emitArch(unsigned Arch);
+ virtual void emitObjectArch(unsigned Arch);
virtual void emitFPU(unsigned FPU);
virtual void emitInst(uint32_t Inst, char Suffix = '\0');
virtual void finishAttributeSection();
@@ -249,6 +250,9 @@ void ARMTargetAsmStreamer::emitIntTextAt
void ARMTargetAsmStreamer::emitArch(unsigned Arch) {
OS << "\t.arch\t" << GetArchName(Arch) << "\n";
}
+void ARMTargetAsmStreamer::emitObjectArch(unsigned Arch) {
+ OS << "\t.object_arch\t" << GetArchName(Arch) << '\n';
+}
void ARMTargetAsmStreamer::emitFPU(unsigned FPU) {
OS << "\t.fpu\t" << GetFPUName(FPU) << "\n";
}
@@ -300,6 +304,7 @@ private:
StringRef CurrentVendor;
unsigned FPU;
unsigned Arch;
+ unsigned EmittedArch;
SmallVector<AttributeItem, 64> Contents;
const MCSection *AttributeSection;
@@ -411,6 +416,7 @@ private:
virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
StringRef StringValue);
virtual void emitArch(unsigned Arch);
+ virtual void emitObjectArch(unsigned Arch);
virtual void emitFPU(unsigned FPU);
virtual void emitInst(uint32_t Inst, char Suffix = '\0');
virtual void finishAttributeSection();
@@ -421,8 +427,9 @@ private:
public:
ARMTargetELFStreamer(MCStreamer &S)
- : ARMTargetStreamer(S), CurrentVendor("aeabi"), FPU(ARM::INVALID_FPU),
- Arch(ARM::INVALID_ARCH), AttributeSection(0) {}
+ : ARMTargetStreamer(S), CurrentVendor("aeabi"), FPU(ARM::INVALID_FPU),
+ Arch(ARM::INVALID_ARCH), EmittedArch(ARM::INVALID_ARCH),
+ AttributeSection(0) {}
};
/// Extend the generic ELFStreamer class so that it can emit mapping symbols at
@@ -714,10 +721,17 @@ void ARMTargetELFStreamer::emitIntTextAt
void ARMTargetELFStreamer::emitArch(unsigned Value) {
Arch = Value;
}
+void ARMTargetELFStreamer::emitObjectArch(unsigned Value) {
+ EmittedArch = Value;
+}
void ARMTargetELFStreamer::emitArchDefaultAttributes() {
using namespace ARMBuildAttrs;
+
setAttributeItem(CPU_name, GetArchDefaultCPUName(Arch), false);
- setAttributeItem(CPU_arch, GetArchDefaultCPUArch(Arch), false);
+ if (EmittedArch == ARM::INVALID_ARCH)
+ setAttributeItem(CPU_arch, GetArchDefaultCPUArch(Arch), false);
+ else
+ setAttributeItem(CPU_arch, GetArchDefaultCPUArch(EmittedArch), false);
switch (Arch) {
case ARM::ARMV2:
Added: llvm/trunk/test/MC/ARM/directive-object_arch-2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/directive-object_arch-2.s?rev=200451&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/directive-object_arch-2.s (added)
+++ llvm/trunk/test/MC/ARM/directive-object_arch-2.s Wed Jan 29 22:46:41 2014
@@ -0,0 +1,22 @@
+@ RUN: llvm-mc -triple armv7-eabi -filetype obj -o - %s \
+@ RUN: | llvm-readobj -arm-attributes | FileCheck %s
+
+ .syntax unified
+
+ .object_arch armv4
+ .arch armv7
+
+@ CHECK: FileAttributes {
+@ CHECK: Attribute {
+@ CHECK: Tag: 5
+@ CHECK: TagName: CPU_name
+@ CHECK: Value: 7
+@ CHECK: }
+@ CHECK: Attribute {
+@ CHECK: Tag: 6
+@ CHEKC: Value: 1
+@ CHECK: TagName: CPU_arch
+@ CHECK: Description: ARM v4
+@ CHECK: }
+@ CHECK: }
+
Added: llvm/trunk/test/MC/ARM/directive-object_arch-3.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/directive-object_arch-3.s?rev=200451&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/directive-object_arch-3.s (added)
+++ llvm/trunk/test/MC/ARM/directive-object_arch-3.s Wed Jan 29 22:46:41 2014
@@ -0,0 +1,11 @@
+@ RUN: llvm-mc -triple armv7-eabi -filetype asm -o - %s | FileCheck %s
+
+ .syntax unified
+
+ .arch armv7
+ .object_arch armv4
+
+@ CHECK: .text
+@ CHECK: .arch armv7
+@ CHECK: .object_arch armv4
+
Added: llvm/trunk/test/MC/ARM/directive-object_arch-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/directive-object_arch-diagnostics.s?rev=200451&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/directive-object_arch-diagnostics.s (added)
+++ llvm/trunk/test/MC/ARM/directive-object_arch-diagnostics.s Wed Jan 29 22:46:41 2014
@@ -0,0 +1,23 @@
+@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null %s 2>&1 \
+@ RUN: | FileCheck %s
+
+ .syntax unified
+
+ .object_arch i686
+
+@ CHECK: error: unknown architecture 'i686'
+@ CHECK: .object_arch i686
+@ CHECK: ^
+
+ .object_arch armv4!
+
+@ CHECK: error: unexpected token
+@ CHECK: .object_arch armv4!
+@ CHECK: ^
+
+ .object_arch, invalid
+
+@ CHECK: error: unexpected token
+@ CHECK: .object_arch, invalid
+@ CHECK: ^
+
Added: llvm/trunk/test/MC/ARM/directive-object_arch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/directive-object_arch.s?rev=200451&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/directive-object_arch.s (added)
+++ llvm/trunk/test/MC/ARM/directive-object_arch.s Wed Jan 29 22:46:41 2014
@@ -0,0 +1,22 @@
+@ RUN: llvm-mc -triple armv7-eabi -filetype obj -o - %s \
+@ RUN: | llvm-readobj -arm-attributes | FileCheck %s
+
+ .syntax unified
+
+ .arch armv7
+ .object_arch armv4
+
+@ CHECK: FileAttributes {
+@ CHECK: Attribute {
+@ CHECK: Tag: 5
+@ CHECK: TagName: CPU_name
+@ CHECK: Value: 7
+@ CHECK: }
+@ CHECK: Attribute {
+@ CHECK: Tag: 6
+@ CHEKC: Value: 1
+@ CHECK: TagName: CPU_arch
+@ CHECK: Description: ARM v4
+@ CHECK: }
+@ CHECK: }
+
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