[llvm] r200348 - Explictly pass MCSubtargetInfo to MCCodeEmitter::EncodeInstruction()
David Woodhouse
dwmw2 at infradead.org
Tue Jan 28 15:13:08 PST 2014
Author: dwmw2
Date: Tue Jan 28 17:13:07 2014
New Revision: 200348
URL: http://llvm.org/viewvc/llvm-project?rev=200348&view=rev
Log:
Explictly pass MCSubtargetInfo to MCCodeEmitter::EncodeInstruction()
Modified:
llvm/trunk/include/llvm/MC/MCCodeEmitter.h
llvm/trunk/lib/MC/MCAsmStreamer.cpp
llvm/trunk/lib/MC/MCAssembler.cpp
llvm/trunk/lib/MC/MCELFStreamer.cpp
llvm/trunk/lib/MC/MCMachOStreamer.cpp
llvm/trunk/lib/MC/MCObjectStreamer.cpp
llvm/trunk/lib/MC/MCPureStreamer.cpp
llvm/trunk/lib/MC/WinCOFFStreamer.cpp
llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp
llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
llvm/trunk/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp
llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
Modified: llvm/trunk/include/llvm/MC/MCCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCCodeEmitter.h?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCCodeEmitter.h (original)
+++ llvm/trunk/include/llvm/MC/MCCodeEmitter.h Tue Jan 28 17:13:07 2014
@@ -15,6 +15,7 @@
namespace llvm {
class MCFixup;
class MCInst;
+class MCSubtargetInfo;
class raw_ostream;
template<typename T> class SmallVectorImpl;
@@ -35,7 +36,8 @@ public:
/// EncodeInstruction - Encode the given \p Inst to bytes on the output
/// stream \p OS.
virtual void EncodeInstruction(const MCInst &Inst, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const = 0;
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const = 0;
};
} // End llvm namespace
Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Tue Jan 28 17:13:07 2014
@@ -104,7 +104,7 @@ public:
virtual void AddComment(const Twine &T);
/// AddEncodingComment - Add a comment showing the encoding of an instruction.
- virtual void AddEncodingComment(const MCInst &Inst);
+ virtual void AddEncodingComment(const MCInst &Inst, const MCSubtargetInfo &);
/// GetCommentOS - Return a raw_ostream that comments can be written to.
/// Unlike AddComment, you are required to terminate comments with \n if you
@@ -1234,12 +1234,13 @@ void MCAsmStreamer::EmitWin64EHEndProlog
EmitEOL();
}
-void MCAsmStreamer::AddEncodingComment(const MCInst &Inst) {
+void MCAsmStreamer::AddEncodingComment(const MCInst &Inst,
+ const MCSubtargetInfo &STI) {
raw_ostream &OS = GetCommentOS();
SmallString<256> Code;
SmallVector<MCFixup, 4> Fixups;
raw_svector_ostream VecOS(Code);
- Emitter->EncodeInstruction(Inst, VecOS, Fixups);
+ Emitter->EncodeInstruction(Inst, VecOS, Fixups, STI);
VecOS.flush();
// If we are showing fixups, create symbolic markers in the encoded
@@ -1324,7 +1325,7 @@ void MCAsmStreamer::EmitInstruction(cons
// Show the encoding in a comment if we have a code emitter.
if (Emitter)
- AddEncodingComment(Inst);
+ AddEncodingComment(Inst, STI);
// Show the MCInst if enabled.
if (ShowInst) {
Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Tue Jan 28 17:13:07 2014
@@ -875,7 +875,7 @@ bool MCAssembler::relaxInstruction(MCAsm
SmallVector<MCFixup, 4> Fixups;
SmallString<256> Code;
raw_svector_ostream VecOS(Code);
- getEmitter().EncodeInstruction(Relaxed, VecOS, Fixups);
+ getEmitter().EncodeInstruction(Relaxed, VecOS, Fixups, F.getSubtargetInfo());
VecOS.flush();
// Update the fragment.
Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCELFStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCELFStreamer.cpp Tue Jan 28 17:13:07 2014
@@ -412,7 +412,7 @@ void MCELFStreamer::EmitInstToData(const
SmallVector<MCFixup, 4> Fixups;
SmallString<256> Code;
raw_svector_ostream VecOS(Code);
- Assembler.getEmitter().EncodeInstruction(Inst, VecOS, Fixups);
+ Assembler.getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
VecOS.flush();
for (unsigned i = 0, e = Fixups.size(); i != e; ++i)
Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Tue Jan 28 17:13:07 2014
@@ -371,7 +371,7 @@ void MCMachOStreamer::EmitInstToData(con
SmallVector<MCFixup, 4> Fixups;
SmallString<256> Code;
raw_svector_ostream VecOS(Code);
- getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups);
+ getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
VecOS.flush();
// Add the fixups and data.
Modified: llvm/trunk/lib/MC/MCObjectStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectStreamer.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCObjectStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCObjectStreamer.cpp Tue Jan 28 17:13:07 2014
@@ -235,7 +235,8 @@ void MCObjectStreamer::EmitInstToFragmen
SmallString<128> Code;
raw_svector_ostream VecOS(Code);
- getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, IF->getFixups());
+ getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, IF->getFixups(),
+ STI);
VecOS.flush();
IF->getContents().append(Code.begin(), Code.end());
}
Modified: llvm/trunk/lib/MC/MCPureStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCPureStreamer.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCPureStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCPureStreamer.cpp Tue Jan 28 17:13:07 2014
@@ -191,7 +191,7 @@ void MCPureStreamer::EmitInstToFragment(
SmallVector<MCFixup, 4> Fixups;
SmallString<256> Code;
raw_svector_ostream VecOS(Code);
- getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups);
+ getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
VecOS.flush();
IF->getContents() = Code;
@@ -205,7 +205,7 @@ void MCPureStreamer::EmitInstToData(cons
SmallVector<MCFixup, 4> Fixups;
SmallString<256> Code;
raw_svector_ostream VecOS(Code);
- getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups);
+ getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
VecOS.flush();
// Add the fixups and data.
Modified: llvm/trunk/lib/MC/WinCOFFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/WinCOFFStreamer.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/MC/WinCOFFStreamer.cpp (original)
+++ llvm/trunk/lib/MC/WinCOFFStreamer.cpp Tue Jan 28 17:13:07 2014
@@ -84,7 +84,7 @@ private:
SmallVector<MCFixup, 4> Fixups;
SmallString<256> Code;
raw_svector_ostream VecOS(Code);
- getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups);
+ getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
VecOS.flush();
// Add the fixups and data.
Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp Tue Jan 28 17:13:07 2014
@@ -121,7 +121,8 @@ public:
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const;
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
template<int hasRs, int hasRt2> unsigned
fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue) const;
@@ -545,7 +546,8 @@ MCCodeEmitter *llvm::createAArch64MCCode
void AArch64MCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const {
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
if (MI.getOpcode() == AArch64::TLSDESCCALL) {
// This is a directive which applies an R_AARCH64_TLSDESC_CALL to the
// following (BLR) instruction. It doesn't emit any code itself so it
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Tue Jan 28 17:13:07 2014
@@ -334,7 +334,8 @@ public:
}
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const;
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
};
} // end anonymous namespace
@@ -1539,7 +1540,8 @@ getShiftRight64Imm(const MCInst &MI, uns
void ARMMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const {
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
// Pseudo instructions don't get encoded.
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
uint64_t TSFlags = Desc.TSFlags;
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Tue Jan 28 17:13:07 2014
@@ -71,7 +71,8 @@ public:
}
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const;
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
// getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction.
@@ -215,7 +216,8 @@ static void LowerDextDins(MCInst& InstIn
/// Size the instruction with Desc.getSize().
void MipsMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const
{
// Non-pseudo instructions that get changed for direct object
Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp Tue Jan 28 17:13:07 2014
@@ -76,7 +76,8 @@ public:
uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups) const;
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const {
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
// For fast-isel, a float COPY_TO_REGCLASS can survive this long.
// It's just a nop to keep the register classes happy, so don't
// generate anything.
Modified: llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp Tue Jan 28 17:13:07 2014
@@ -99,7 +99,8 @@ void AMDGPUAsmPrinter::EmitInstruction(c
MCObjectStreamer &ObjStreamer = (MCObjectStreamer &)OutStreamer;
MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
- InstEmitter.EncodeInstruction(TmpInst, CodeStream, Fixups);
+ InstEmitter.EncodeInstruction(TmpInst, CodeStream, Fixups,
+ TM.getSubtarget<MCSubtargetInfo>());
CodeStream.flush();
HexLines.resize(HexLines.size() + 1);
Modified: llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp Tue Jan 28 17:13:07 2014
@@ -44,7 +44,8 @@ public:
/// \brief Encode the instruction and write it to the OS.
virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const;
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
/// \returns the encoding for an MCOperand.
virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
@@ -87,7 +88,8 @@ MCCodeEmitter *llvm::createR600MCCodeEmi
}
void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const {
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
if (MI.getOpcode() == AMDGPU::RETURN ||
MI.getOpcode() == AMDGPU::FETCH_CLAUSE ||
Modified: llvm/trunk/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp Tue Jan 28 17:13:07 2014
@@ -55,7 +55,8 @@ public:
/// \brief Encode the instruction and write it to the OS.
virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const;
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
/// \returns the encoding for an MCOperand.
virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
@@ -125,7 +126,8 @@ uint32_t SIMCCodeEmitter::getLitEncoding
}
void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const {
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups);
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp Tue Jan 28 17:13:07 2014
@@ -39,7 +39,8 @@ public:
~SparcMCCodeEmitter() {}
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const;
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
// getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction.
@@ -68,7 +69,8 @@ MCCodeEmitter *llvm::createSparcMCCodeEm
void SparcMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const {
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
unsigned Bits = getBinaryCodeForInstr(MI, Fixups);
// Output the constant in big endian byte order.
Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp Tue Jan 28 17:13:07 2014
@@ -35,7 +35,8 @@ public:
// OVerride MCCodeEmitter.
virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const
LLVM_OVERRIDE;
private:
@@ -91,7 +92,8 @@ MCCodeEmitter *llvm::createSystemZMCCode
void SystemZMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const {
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
unsigned Size = MCII.get(MI.getOpcode()).getSize();
// Big-endian insertion of Size bytes.
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=200348&r1=200347&r2=200348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Tue Jan 28 17:13:07 2014
@@ -152,7 +152,8 @@ public:
SmallVectorImpl<MCFixup> &Fixups) const;
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const;
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
const MCInst &MI, const MCInstrDesc &Desc,
@@ -1268,7 +1269,8 @@ void X86MCCodeEmitter::EmitOpcodePrefix(
void X86MCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const {
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
unsigned Opcode = MI.getOpcode();
const MCInstrDesc &Desc = MCII.get(Opcode);
uint64_t TSFlags = Desc.TSFlags;
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