[PATCH] Fix unsupported addressing mode assertion for pld

[David Peixotto]

  Updated commit message

  It had an outdated comment about the test file.

http://llvm-reviews.chandlerc.com/D2622

CHANGE SINCE LAST DIFF
  http://llvm-reviews.chandlerc.com/D2622?vs=6656&id=6658#toc

Files:
  lib/Target/ARM/ARMInstrFormats.td
  lib/Target/ARM/ARMInstrInfo.td
  test/CodeGen/ARM/prefetch-thumb.ll
  test/CodeGen/ARM/prefetch.ll

Index: lib/Target/ARM/ARMInstrFormats.td
===================================================================
--- lib/Target/ARM/ARMInstrFormats.td
+++ lib/Target/ARM/ARMInstrFormats.td
@@ -477,6 +477,10 @@
           string asm, list<dag> pattern>
   : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
        asm, "", pattern>;
+class AXIM<dag oops, dag iops, AddrMode am, Format f, InstrItinClass itin,
+          string asm, list<dag> pattern>
+  : XI<oops, iops, am, 4, IndexModeNone, f, itin,
+       asm, "", pattern>;
 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
             string opc, string asm, list<dag> pattern>
   : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
Index: lib/Target/ARM/ARMInstrInfo.td
===================================================================
--- lib/Target/ARM/ARMInstrInfo.td
+++ lib/Target/ARM/ARMInstrInfo.td
@@ -1775,8 +1775,8 @@
 // Preload signals the memory system of possible future data/instruction access.
 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
 
-  def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
-                !strconcat(opc, "\t$addr"),
+  def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
+                IIC_Preload, !strconcat(opc, "\t$addr"),
                 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
                 Sched<[WritePreLd]> {
     bits<4> Rt;
Index: test/CodeGen/ARM/prefetch-thumb.ll
===================================================================
--- test/CodeGen/ARM/prefetch-thumb.ll
+++ /dev/null
@@ -1,22 +0,0 @@
-; RUN: llc < %s -march=thumb -mattr=+v7         | FileCheck %s -check-prefix=THUMB2
-; TODO: This test case will be merged back into prefetch.ll when ARM mode issue is solved.
-
-declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
-
-define void @t6() {
-entry:
-;ARM: t6:
-;ARM: pld [sp]
-;ARM: pld [sp, #50]
-
-;THUMB2: t6:
-;THUMB2: pld [sp]
-;THUMB2: pld [sp, #50]
-
-%red = alloca [100 x i8], align 1
-%0 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 0
-%1 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 50
-call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1)
-call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1)
-ret void
-}
Index: test/CodeGen/ARM/prefetch.ll
===================================================================
--- test/CodeGen/ARM/prefetch.ll
+++ test/CodeGen/ARM/prefetch.ll
@@ -75,3 +75,21 @@
   tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 0 )
   ret void
 }
+
+define void @t6() {
+entry:
+;ARM-LABEL: t6:
+;ARM: pld [sp]
+;ARM: pld [sp, #50]
+
+;THUMB2-LABEL: t6:
+;THUMB2: pld [sp]
+;THUMB2: pld [sp, #50]
+
+%red = alloca [100 x i8], align 1
+%0 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 0
+%1 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 50
+call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1)
+call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1)
+ret void
+}
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