[llvm] r199461 - [AArch64]Fix the problem can't select concat_vectors of two v1i32 types.
Hao Liu
Hao.Liu at arm.com
Wed Jan 22 18:27:10 PST 2014
Hi Chad,
Sorry for the delay.
You are right. It's better to have CHECK.
As the scalar_to_vector has no instruction, I add another intrinsic and use
"CHECK" and "CHECK-NEXT ret".
Committed in http://llvm.org/viewvc/llvm-project?rev=199861&view=rev.
Thanks,
-Hao
-----Original Message-----
From: Chad Rosier [mailto:mcrosier at codeaurora.org]
Sent: Sunday, January 19, 2014 2:15 AM
To: Hao Liu
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm] r199461 - [AArch64]Fix the problem can't select
concat_vectors of two v1i32 types.
Hi Hao,
I noticed that the last two test cases don't have CHECK directives. It
would be good to add those checks.
Chad
> Author: haoliu
> Date: Thu Jan 16 23:44:46 2014
> New Revision: 199461
>
> URL: http://llvm.org/viewvc/llvm-project?rev=199461&view=rev
> Log:
> [AArch64]Fix the problem can't select concat_vectors of two v1i32 types.
> Also fix the problem can't select scalar_to_vector from f32 to
> v2f32/v4f32.
>
> Modified:
> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
> llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td
> llvm/trunk/test/CodeGen/AArch64/neon-copy.ll
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArc
> h64ISelLowering.cpp?rev=199461&r1=199460&r2=199461&view=diff
> ======================================================================
> ========
> --- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Thu Jan 16
> 23:44:46 2014
> @@ -324,13 +324,11 @@ AArch64TargetLowering::AArch64TargetLowe
> setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1f64, Custom);
> setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
>
> + setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i32, Legal);
> setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Legal);
> setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Legal);
> setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Legal);
> setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Legal);
> - setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Legal);
> - setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Legal);
> - setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Legal);
> setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Legal);
> setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Legal);
>
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArc
> h64InstrNEON.td?rev=199461&r1=199460&r2=199461&view=diff
> ======================================================================
> ========
> --- llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td Thu Jan 16
> +++ 23:44:46
> 2014
> @@ -6888,15 +6888,10 @@ def : Pat<(v4i32 (scalar_to_vector GPR32 def
> : Pat<(v2i64 (scalar_to_vector GPR64:$Rn)),
> (INSdx (v2i64 (IMPLICIT_DEF)), $Rn, (i64 0))>;
>
> -def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
> - (v2i32 (EXTRACT_SUBREG (v16i8
> - (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
> - sub_64))>;
> -
> -def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
> - (v2i32 (EXTRACT_SUBREG (v16i8
> - (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
> - sub_64))>;
> +def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
> + (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32)>; def :
> +Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
> + (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32)>;
>
> def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
> (v1f64 FPR64:$Rn)>;
> @@ -7063,6 +7058,11 @@ defm : Concat_Vector_Pattern<v2i64, v1i6 defm
> : Concat_Vector_Pattern<v4f32, v2f32>; defm :
> Concat_Vector_Pattern<v2f64, v1f64>;
>
> +def : Pat<(v2i32 (concat_vectors (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rn))),
> + (DUPELT2s (v4i32 (SUBREG_TO_REG(i64 0), $Rn, sub_32)), 0)>;
> +def : Pat<(v2i32 (concat_vectors undef, (v1i32 FPR32:$Rn))),
> + (DUPELT2s (v4i32 (SUBREG_TO_REG(i64 0), $Rn, sub_32)), 0)>;
> +
> //patterns for EXTRACT_SUBVECTOR
> def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
> (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
>
> Modified: llvm/trunk/test/CodeGen/AArch64/neon-copy.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ne
> on-copy.ll?rev=199461&r1=199460&r2=199461&view=diff
> ======================================================================
> ========
> --- llvm/trunk/test/CodeGen/AArch64/neon-copy.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/neon-copy.ll Thu Jan 16 23:44:46
> +++ 2014
> @@ -948,3 +948,35 @@ entry:
> ret <2 x i32> %vecinit1.i
> }
>
> +define <2 x i32> @test_concat_undef_v1i32(<1 x i32> %a) { ;
> +CHECK-LABEL: test_concat_undef_v1i32:
> +; CHECK: dup v{{[0-9]+}}.2s, v{{[0-9]+}}.s[0]
> +entry:
> + %0 = extractelement <1 x i32> %a, i32 0
> + %vecinit1.i = insertelement <2 x i32> undef, i32 %0, i32 1
> + ret <2 x i32> %vecinit1.i
> +}
> +
> +define <2 x i32> @test_concat_v1i32_v1i32(<1 x i32> %a) { ;
> +CHECK-LABEL: test_concat_v1i32_v1i32:
> +; CHECK: dup v{{[0-9]+}}.2s, v{{[0-9]+}}.s[0]
> +entry:
> + %0 = extractelement <1 x i32> %a, i32 0
> + %vecinit.i = insertelement <2 x i32> undef, i32 %0, i32 0
> + %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %0, i32 1
> + ret <2 x i32> %vecinit1.i
> +}
> +
> +define <2 x float> @test_scalar_to_vector_f32_to_v2f32(<1 x float>
> +%a) {
> +entry:
> + %0 = extractelement <1 x float> %a, i32 0
> + %vecinit1.i = insertelement <2 x float> undef, float %0, i32 0
> + ret <2 x float> %vecinit1.i
> +}
> +
> +define <4 x float> @test_scalar_to_vector_f32_to_v4f32(<1 x float>
> +%a) {
> +entry:
> + %0 = extractelement <1 x float> %a, i32 0
> + %vecinit1.i = insertelement <4 x float> undef, float %0, i32 0
> + ret <4 x float> %vecinit1.i
> +}
> \ No newline at end of file
>
>
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