[llvm] r199391 - [mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
Andrew Trick
atrick at apple.com
Fri Jan 17 11:15:21 PST 2014
On Jan 16, 2014, at 6:27 AM, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote:
> Author: dsanders
> Date: Thu Jan 16 08:27:20 2014
> New Revision: 199391
>
> URL: http://llvm.org/viewvc/llvm-project?rev=199391&view=rev
> Log:
> [mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
>
> IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
> II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
> II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
> II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
> II_SR[AL]V, II_SUBU, II_XOR
>
> No functional change since the InstrItinData's have been duplicated.
>
> This is necessary because the classes are shared between all schedulers.
>
> Once this patch series is committed there will be an InstrItinClass for
> each mnemonic with minimal grouping. This does increase the size of the
> itinerary tables for each MIPS scheduler but we have a few options for dealing
> with that later. These options include reducing the number of classes once
> we see the best way to simplify them, or by extending tablegen to be able
> to compress the table by eliminating duplicates entries, etc.
I know the MIPS itinerary classes have been around a long time and your pretty far into rewriting the instruction definitions. I just want to encourage anyone scheduling for a new subtarget to use the new machine model instead of defining a ProcessorItinerary. It provides a lot more flexibility in customizing your subtarget without rewriting instruction definitions. Ultimately it would be nice to migrate all targets away from itineraries since the new model should handle everything. As a migration strategy you can still use the itinerary classes and map them to a new machine model, it’s just a redundant level of abstraction. The ARM A9 target does this using ItinRW definitions.
Independent of the machine model/itinerary, please try to use the new MI scheduler. It supports pre and post RA scheduling with either the (old) itineraries or new machine model.
Don’t hesitate to add the target hooks that you need to get the right combination of schedulers working on your target. I’m here to answer questions about the MI scheduler or new machine model, especially when you’re initially trying to navigate the infrastructure (there are many ways you can set things up for your subtarget, so figuring out the “right” way can be confusing). I can also help explain why the scheduler is making certain decisions but naturally won’t be able to explain why it’s a good or bad on your subtarget.
-Andy
> Modified:
> llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
> llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
> llvm/trunk/lib/Target/Mips/MipsCondMov.td
> llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
> llvm/trunk/lib/Target/Mips/MipsSchedule.td
>
> Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=199391&r1=199390&r2=199391&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Thu Jan 16 08:27:20 2014
> @@ -116,21 +116,21 @@ let DecoderNamespace = "MicroMips", Pred
> MULT_FM_MM<0x2ec>;
>
> /// Shift Instructions
> - def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd>,
> + def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
> SRA_FM_MM<0, 0>;
> - def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd>,
> + def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
> SRA_FM_MM<0x40, 0>;
> - def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd>,
> + def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
> SRA_FM_MM<0x80, 0>;
> - def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd>,
> + def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
> SRLV_FM_MM<0x10, 0>;
> - def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd>,
> + def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
> SRLV_FM_MM<0x50, 0>;
> - def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd>,
> + def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
> SRLV_FM_MM<0x90, 0>;
> - def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd>,
> + def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
> SRA_FM_MM<0xc0, 0>;
> - def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd>,
> + def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
> SRLV_FM_MM<0xd0, 0>;
>
> /// Load and Store Instructions - aligned
>
> Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=199391&r1=199390&r2=199391&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Thu Jan 16 08:27:20 2014
> @@ -54,7 +54,7 @@ let isPseudo = 1, isCodeGenOnly = 1 in {
> let DecoderNamespace = "Mips64" in {
> /// Arithmetic Instructions (ALU Immediate)
> def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>;
> -def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, IIArith,
> +def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
> immSExt16, add>,
> ADDI_FM<0x19>, IsAsCheapAsAMove;
>
> @@ -77,41 +77,48 @@ def LUi64 : LoadUpper<"lui", GPR64Opnd
>
> /// Arithmetic Instructions (3-Operand, R-Type)
> def DADD : ArithLogicR<"dadd", GPR64Opnd>, ADD_FM<0, 0x2c>;
> -def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, IIArith, add>,
> +def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
> ADD_FM<0, 0x2d>;
> -def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, IIArith, sub>,
> +def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>,
> ADD_FM<0, 0x2f>;
>
> let isCodeGenOnly = 1 in {
> def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
> def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
> -def AND64 : ArithLogicR<"and", GPR64Opnd, 1, IIArith, and>, ADD_FM<0, 0x24>;
> -def OR64 : ArithLogicR<"or", GPR64Opnd, 1, IIArith, or>, ADD_FM<0, 0x25>;
> -def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, IIArith, xor>, ADD_FM<0, 0x26>;
> +def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
> +def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
> +def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
> def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
> }
>
> /// Shift Instructions
> -def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, shl, immZExt6>,
> +def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
> SRA_FM<0x38, 0>;
> -def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, srl, immZExt6>,
> +def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
> SRA_FM<0x3a, 0>;
> -def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, sra, immZExt6>,
> +def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
> SRA_FM<0x3b, 0>;
> -def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, shl>, SRLV_FM<0x14, 0>;
> -def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, srl>, SRLV_FM<0x16, 0>;
> -def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, sra>, SRLV_FM<0x17, 0>;
> -def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd>, SRA_FM<0x3c, 0>;
> -def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd>, SRA_FM<0x3e, 0>;
> -def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd>, SRA_FM<0x3f, 0>;
> +def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
> + SRLV_FM<0x14, 0>;
> +def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
> + SRLV_FM<0x16, 0>;
> +def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
> + SRLV_FM<0x17, 0>;
> +def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
> + SRA_FM<0x3c, 0>;
> +def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
> + SRA_FM<0x3e, 0>;
> +def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
> + SRA_FM<0x3f, 0>;
>
> // Rotate Instructions
> let Predicates = [HasMips64r2, HasStdEnc] in {
> - def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, rotr, immZExt6>,
> - SRA_FM<0x3a, 1>;
> - def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, rotr>,
> + def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
> + immZExt6>, SRA_FM<0x3a, 1>;
> + def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
> SRLV_FM<0x16, 1>;
> - def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd>, SRA_FM<0x3e, 1>;
> + def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
> + SRA_FM<0x3e, 1>;
> }
>
> /// Load and Store Instructions
> @@ -215,11 +222,11 @@ def DINSM : InsBase<"dinsm", GPR64Opnd,
>
> let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
> def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
> - "dsll\t$rd, $rt, 32", [], IIArith>;
> + "dsll\t$rd, $rt, 32", [], II_DSLL>;
> def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
> - "sll\t$rd, $rt, 0", [], IIArith>;
> + "sll\t$rd, $rt, 0", [], II_SLL>;
> def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
> - "sll\t$rd, $rt, 0", [], IIArith>;
> + "sll\t$rd, $rt, 0", [], II_SLL>;
> }
> }
> //===----------------------------------------------------------------------===//
>
> Modified: llvm/trunk/lib/Target/Mips/MipsCondMov.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCondMov.td?rev=199391&r1=199390&r2=199391&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsCondMov.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsCondMov.td Thu Jan 16 08:27:20 2014
> @@ -103,27 +103,27 @@ multiclass MovnPats<RegisterClass CRC, R
> }
>
> // Instantiation of instructions.
> -def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, IIArith>,
> +def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>,
> ADD_FM<0, 0xa>;
>
> let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
> - def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, IIArith>,
> + def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>,
> ADD_FM<0, 0xa>;
> - def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, IIArith>,
> + def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>,
> ADD_FM<0, 0xa>;
> - def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, IIArith>,
> + def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, II_MOVZ>,
> ADD_FM<0, 0xa>;
> }
>
> -def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, IIArith>,
> +def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>,
> ADD_FM<0, 0xb>;
>
> let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
> - def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, IIArith>,
> + def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>,
> ADD_FM<0, 0xb>;
> - def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, IIArith>,
> + def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>,
> ADD_FM<0, 0xb>;
> - def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, IIArith>,
> + def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>,
> ADD_FM<0, 0xb>;
> }
>
> @@ -161,18 +161,18 @@ let Predicates = [IsFP64bit, HasStdEnc],
> }
> }
>
> -def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, IIArith, MipsCMovFP_T>,
> +def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,
> CMov_F_I_FM<1>;
>
> let isCodeGenOnly = 1 in
> -def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, IIArith, MipsCMovFP_T>,
> +def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>,
> CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]>;
>
> -def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, IIArith, MipsCMovFP_F>,
> +def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
> CMov_F_I_FM<0>;
>
> let isCodeGenOnly = 1 in
> -def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, IIArith, MipsCMovFP_F>,
> +def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>,
> CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]>;
>
> def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, IIFmove, MipsCMovFP_T>,
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=199391&r1=199390&r2=199391&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Jan 16 08:27:20 2014
> @@ -448,28 +448,30 @@ class MArithR<string opstr, bit isComm =
> class LogicNOR<string opstr, RegisterOperand RO>:
> InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
> !strconcat(opstr, "\t$rd, $rs, $rt"),
> - [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
> + [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
> let isCommutable = 1;
> }
>
> // Shifts
> class shift_rotate_imm<string opstr, Operand ImmOpnd,
> - RegisterOperand RO, SDPatternOperator OpNode = null_frag,
> + RegisterOperand RO, InstrItinClass itin,
> + SDPatternOperator OpNode = null_frag,
> SDPatternOperator PF = null_frag> :
> InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
> !strconcat(opstr, "\t$rd, $rt, $shamt"),
> - [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
> + [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr>;
>
> -class shift_rotate_reg<string opstr, RegisterOperand RO,
> +class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
> SDPatternOperator OpNode = null_frag>:
> InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
> !strconcat(opstr, "\t$rd, $rt, $rs"),
> - [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
> + [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
> + opstr>;
>
> // Load Upper Imediate
> class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
> InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
> - [], IIArith, FrmI, opstr>, IsAsCheapAsAMove {
> + [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
> let neverHasSideEffects = 1;
> let isReMaterializable = 1;
> }
> @@ -756,12 +758,12 @@ class EffectiveAddress<string opstr, Reg
> // Count Leading Ones/Zeros in Word
> class CountLeading0<string opstr, RegisterOperand RO>:
> InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
> - [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR, opstr>,
> + [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
> Requires<[HasBitCount, HasStdEnc]>;
>
> class CountLeading1<string opstr, RegisterOperand RO>:
> InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
> - [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR, opstr>,
> + [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
> Requires<[HasBitCount, HasStdEnc]>;
>
>
> @@ -783,7 +785,7 @@ class SubwordSwap<string opstr, Register
> // Read Hardware
> class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
> InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
> - IIArith, FrmR>;
> + II_RDHWR, FrmR>;
>
> // Ext and Ins
> class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
> @@ -900,7 +902,7 @@ let isPseudo = 1, isCodeGenOnly = 1 in {
> //===----------------------------------------------------------------------===//
>
> /// Arithmetic Instructions (ALU Immediate)
> -def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16,
> +def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
> add>,
> ADDI_FM<0x9>, IsAsCheapAsAMove;
> def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
> @@ -920,9 +922,9 @@ def XORi : MMRel, ArithLogicI<"xori", u
> def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
>
> /// Arithmetic Instructions (3-Operand, R-Type)
> -def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>,
> +def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
> ADD_FM<0, 0x21>;
> -def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
> +def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
> ADD_FM<0, 0x23>;
> let Defs = [HI0, LO0] in
> def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
> @@ -940,22 +942,24 @@ def XOR : MMRel, ArithLogicR<"xor", GP
> def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
>
> /// Shift Instructions
> -def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, shl, immZExt5>,
> - SRA_FM<0, 0>;
> -def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, srl, immZExt5>,
> - SRA_FM<2, 0>;
> -def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, sra, immZExt5>,
> - SRA_FM<3, 0>;
> -def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>;
> -def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>;
> -def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>;
> +def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
> + immZExt5>, SRA_FM<0, 0>;
> +def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
> + immZExt5>, SRA_FM<2, 0>;
> +def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
> + immZExt5>, SRA_FM<3, 0>;
> +def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
> + SRLV_FM<4, 0>;
> +def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
> + SRLV_FM<6, 0>;
> +def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
> + SRLV_FM<7, 0>;
>
> // Rotate Instructions
> let Predicates = [HasMips32r2, HasStdEnc] in {
> - def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, rotr,
> - immZExt5>,
> - SRA_FM<2, 1>;
> - def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>,
> + def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
> + immZExt5>, SRA_FM<2, 1>;
> + def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
> SRLV_FM<6, 1>;
> }
>
>
> Modified: llvm/trunk/lib/Target/Mips/MipsSchedule.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSchedule.td?rev=199391&r1=199390&r2=199391&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsSchedule.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsSchedule.td Thu Jan 16 08:27:20 2014
> @@ -17,7 +17,6 @@ def IMULDIV : FuncUnit;
> // Instruction Itinerary classes used for Mips
> //===----------------------------------------------------------------------===//
> def IIAlu : InstrItinClass;
> -def IIArith : InstrItinClass;
> def IILogic : InstrItinClass;
> def IILoad : InstrItinClass;
> def IIStore : InstrItinClass;
> @@ -45,12 +44,87 @@ def IIFStore : InstrItinClass;
> def IIFmoveC1 : InstrItinClass;
> def IIPseudo : InstrItinClass;
>
> +def II_ADDI : InstrItinClass;
> +def II_ADDIU : InstrItinClass;
> +def II_ADDU : InstrItinClass;
> +def II_AND : InstrItinClass;
> +def II_CLO : InstrItinClass;
> +def II_CLZ : InstrItinClass;
> +def II_DADDIU : InstrItinClass;
> +def II_DADDU : InstrItinClass;
> +def II_DROTR : InstrItinClass;
> +def II_DROTR32 : InstrItinClass;
> +def II_DROTRV : InstrItinClass;
> +def II_DSLL : InstrItinClass;
> +def II_DSLL32 : InstrItinClass;
> +def II_DSLLV : InstrItinClass;
> +def II_DSRA : InstrItinClass;
> +def II_DSRA32 : InstrItinClass;
> +def II_DSRAV : InstrItinClass;
> +def II_DSRL : InstrItinClass;
> +def II_DSRL32 : InstrItinClass;
> +def II_DSRLV : InstrItinClass;
> +def II_DSUBU : InstrItinClass;
> +def II_LUI : InstrItinClass;
> +def II_MOVF : InstrItinClass;
> +def II_MOVN : InstrItinClass;
> +def II_MOVT : InstrItinClass;
> +def II_MOVZ : InstrItinClass;
> +def II_NOR : InstrItinClass;
> +def II_OR : InstrItinClass;
> +def II_ORI : InstrItinClass;
> +def II_RDHWR : InstrItinClass;
> +def II_ROTR : InstrItinClass;
> +def II_ROTRV : InstrItinClass;
> +def II_SLL : InstrItinClass;
> +def II_SLLV : InstrItinClass;
> +def II_SRA : InstrItinClass;
> +def II_SRAV : InstrItinClass;
> +def II_SRL : InstrItinClass;
> +def II_SRLV : InstrItinClass;
> +def II_SUBU : InstrItinClass;
> +def II_XOR : InstrItinClass;
> +
> //===----------------------------------------------------------------------===//
> // Mips Generic instruction itineraries.
> //===----------------------------------------------------------------------===//
> def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
> InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>,
> - InstrItinData<IIArith , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_AND , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_SLL , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_SRA , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_SRL , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_ROTR , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_SLLV , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_SRAV , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_SRLV , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_ROTRV , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_CLO , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_CLZ , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_DADDIU , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_DADDU , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_DSLL , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_DSRL , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_DSRA , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_DSLLV , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_DSRLV , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_DSRAV , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_DSUBU , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_DROTR , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_DROTRV , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_LUI , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_MOVF , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_MOVN , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_MOVT , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_MOVZ , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_NOR , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_OR , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_RDHWR , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_SUBU , [InstrStage<1, [ALU]>]>,
> + InstrItinData<II_XOR , [InstrStage<1, [ALU]>]>,
> InstrItinData<IILogic , [InstrStage<1, [ALU]>]>,
> InstrItinData<IILoad , [InstrStage<3, [ALU]>]>,
> InstrItinData<IIStore , [InstrStage<1, [ALU]>]>,
>
>
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