[llvm] r199265 - AArch64: don't try to handle [SU]MUL_LOHI nodes

[Tim Northover]

Author: tnorthover
Date: Tue Jan 14 16:53:22 2014
New Revision: 199265

URL: http://llvm.org/viewvc/llvm-project?rev=199265&view=rev
Log:
AArch64: don't try to handle [SU]MUL_LOHI nodes

We should set them to expand for now since there are no patterns
dealing with them. Actually, there are no instructions either so I
doubt they'll ever be acceptable.

Added:
    llvm/trunk/test/CodeGen/AArch64/mul-lohi.ll
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=199265&r1=199264&r2=199265&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Jan 14 16:53:22 2014
@@ -151,6 +151,11 @@ AArch64TargetLowering::AArch64TargetLowe
   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
   setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
 
+  setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
+  setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
+  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
+  setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
+
   setOperationAction(ISD::CTPOP, MVT::i32, Expand);
   setOperationAction(ISD::CTPOP, MVT::i64, Expand);
 

Added: llvm/trunk/test/CodeGen/AArch64/mul-lohi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/mul-lohi.ll?rev=199265&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/mul-lohi.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/mul-lohi.ll Tue Jan 14 16:53:22 2014
@@ -0,0 +1,12 @@
+; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s
+
+define i128 @test_128bitmul(i128 %lhs, i128 %rhs) {
+; CHECK: test_128bitmul:
+; CHECK-DAG: umulh [[CARRY:x[0-9]+]], x0, x2
+; CHECK-DAG: madd [[PART1:x[0-9]+]], x0, x3, [[CARRY]]
+; CHECK: madd x1, x1, x2, [[PART1]]
+; CHECK: mul x0, x0, x2
+
+  %prod = mul i128 %lhs, %rhs
+  ret i128 %prod
+}