[llvm] r198588 - Remove SegOvrBits from X86 TSFlags since they weren't being used.
Craig Topper
craig.topper at gmail.com
Sun Jan 5 22:51:59 PST 2014
Author: ctopper
Date: Mon Jan 6 00:51:58 2014
New Revision: 198588
URL: http://llvm.org/viewvc/llvm-project?rev=198588&view=rev
Log:
Remove SegOvrBits from X86 TSFlags since they weren't being used.
Modified:
llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
llvm/trunk/lib/Target/X86/X86InstrFormats.td
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h?rev=198588&r1=198587&r2=198588&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h Mon Jan 6 00:51:58 2014
@@ -417,16 +417,9 @@ namespace X86II {
LOCKShift = FPTypeShift + 3,
LOCK = 1 << LOCKShift,
- // Segment override prefixes. Currently we just need ability to address
- // stuff in gs and fs segments.
- SegOvrShift = LOCKShift + 1,
- SegOvrMask = 3 << SegOvrShift,
- FS = 1 << SegOvrShift,
- GS = 2 << SegOvrShift,
-
// Execution domain for SSE instructions in bits 23, 24.
// 0 in bits 23-24 means normal, non-SSE instruction.
- SSEDomainShift = SegOvrShift + 2,
+ SSEDomainShift = LOCKShift + 1,
OpcodeShift = SSEDomainShift + 2,
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=198588&r1=198587&r2=198588&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Mon Jan 6 00:51:58 2014
@@ -1123,29 +1123,19 @@ void X86MCCodeEmitter::EmitSegmentOverri
unsigned &CurByte, int MemOperand,
const MCInst &MI,
raw_ostream &OS) const {
- switch (TSFlags & X86II::SegOvrMask) {
- default: llvm_unreachable("Invalid segment!");
- case 0:
- // No segment override, check for explicit one on memory operand.
- if (MemOperand != -1) { // If the instruction has a memory operand.
- switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
- default: llvm_unreachable("Unknown segment register!");
- case 0: break;
- case X86::CS: EmitByte(0x2E, CurByte, OS); break;
- case X86::SS: EmitByte(0x36, CurByte, OS); break;
- case X86::DS: EmitByte(0x3E, CurByte, OS); break;
- case X86::ES: EmitByte(0x26, CurByte, OS); break;
- case X86::FS: EmitByte(0x64, CurByte, OS); break;
- case X86::GS: EmitByte(0x65, CurByte, OS); break;
- }
- }
- break;
- case X86II::FS:
- EmitByte(0x64, CurByte, OS);
- break;
- case X86II::GS:
- EmitByte(0x65, CurByte, OS);
- break;
+ if (MemOperand < 0)
+ return; // No memory operand
+
+ // Check for explicit segment override on memory operand.
+ switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
+ default: llvm_unreachable("Unknown segment register!");
+ case 0: break;
+ case X86::CS: EmitByte(0x2E, CurByte, OS); break;
+ case X86::SS: EmitByte(0x36, CurByte, OS); break;
+ case X86::DS: EmitByte(0x3E, CurByte, OS); break;
+ case X86::ES: EmitByte(0x26, CurByte, OS); break;
+ case X86::FS: EmitByte(0x64, CurByte, OS); break;
+ case X86::GS: EmitByte(0x65, CurByte, OS); break;
}
}
Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=198588&r1=198587&r2=198588&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Mon Jan 6 00:51:58 2014
@@ -774,29 +774,19 @@ template<class CodeEmitter>
void Emitter<CodeEmitter>::emitSegmentOverridePrefix(uint64_t TSFlags,
int MemOperand,
const MachineInstr &MI) const {
- switch (TSFlags & X86II::SegOvrMask) {
- default: llvm_unreachable("Invalid segment!");
- case 0:
- // No segment override, check for explicit one on memory operand.
- if (MemOperand != -1) { // If the instruction has a memory operand.
- switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
- default: llvm_unreachable("Unknown segment register!");
- case 0: break;
- case X86::CS: MCE.emitByte(0x2E); break;
- case X86::SS: MCE.emitByte(0x36); break;
- case X86::DS: MCE.emitByte(0x3E); break;
- case X86::ES: MCE.emitByte(0x26); break;
- case X86::FS: MCE.emitByte(0x64); break;
- case X86::GS: MCE.emitByte(0x65); break;
- }
- }
- break;
- case X86II::FS:
- MCE.emitByte(0x64);
- break;
- case X86II::GS:
- MCE.emitByte(0x65);
- break;
+ if (MemOperand < 0)
+ return; // No memory operand
+
+ // Check for explicit segment override on memory operand.
+ switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
+ default: llvm_unreachable("Unknown segment register!");
+ case 0: break;
+ case X86::CS: MCE.emitByte(0x2E); break;
+ case X86::SS: MCE.emitByte(0x36); break;
+ case X86::DS: MCE.emitByte(0x3E); break;
+ case X86::ES: MCE.emitByte(0x26); break;
+ case X86::FS: MCE.emitByte(0x64); break;
+ case X86::GS: MCE.emitByte(0x65); break;
}
}
Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=198588&r1=198587&r2=198588&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Mon Jan 6 00:51:58 2014
@@ -116,8 +116,6 @@ class OpSize16 { bit hasOpSize16Prefix =
class AdSize { bit hasAdSizePrefix = 1; }
class REX_W { bit hasREX_WPrefix = 1; }
class LOCK { bit hasLockPrefix = 1; }
-class SegFS { bits<2> SegOvrBits = 1; }
-class SegGS { bits<2> SegOvrBits = 2; }
class TB { bits<5> Prefix = 1; }
class REP { bits<5> Prefix = 2; }
class D8 { bits<5> Prefix = 3; }
@@ -199,7 +197,6 @@ class X86Inst<bits<8> opcod, Format f, I
bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
- bits<2> SegOvrBits = 0; // Segment override prefix.
Domain ExeDomain = d;
bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
@@ -231,26 +228,25 @@ class X86Inst<bits<8> opcod, Format f, I
let TSFlags{17-15} = ImmT.Value;
let TSFlags{20-18} = FPForm.Value;
let TSFlags{21} = hasLockPrefix;
- let TSFlags{23-22} = SegOvrBits;
- let TSFlags{25-24} = ExeDomain.Value;
- let TSFlags{33-26} = Opcode;
- let TSFlags{34} = hasVEXPrefix;
- let TSFlags{35} = hasVEX_WPrefix;
- let TSFlags{36} = hasVEX_4VPrefix;
- let TSFlags{37} = hasVEX_4VOp3Prefix;
- let TSFlags{38} = hasVEX_i8ImmReg;
- let TSFlags{39} = hasVEX_L;
- let TSFlags{40} = ignoresVEX_L;
- let TSFlags{41} = hasEVEXPrefix;
- let TSFlags{42} = hasEVEX_K;
- let TSFlags{43} = hasEVEX_Z;
- let TSFlags{44} = hasEVEX_L2;
- let TSFlags{45} = hasEVEX_B;
- let TSFlags{47-46} = EVEX_CD8E;
- let TSFlags{50-48} = EVEX_CD8V;
- let TSFlags{51} = has3DNow0F0FOpcode;
- let TSFlags{52} = hasMemOp4Prefix;
- let TSFlags{53} = hasXOP_Prefix;
+ let TSFlags{23-22} = ExeDomain.Value;
+ let TSFlags{31-24} = Opcode;
+ let TSFlags{32} = hasVEXPrefix;
+ let TSFlags{33} = hasVEX_WPrefix;
+ let TSFlags{34} = hasVEX_4VPrefix;
+ let TSFlags{35} = hasVEX_4VOp3Prefix;
+ let TSFlags{36} = hasVEX_i8ImmReg;
+ let TSFlags{37} = hasVEX_L;
+ let TSFlags{38} = ignoresVEX_L;
+ let TSFlags{39} = hasEVEXPrefix;
+ let TSFlags{40} = hasEVEX_K;
+ let TSFlags{41} = hasEVEX_Z;
+ let TSFlags{42} = hasEVEX_L2;
+ let TSFlags{43} = hasEVEX_B;
+ let TSFlags{45-44} = EVEX_CD8E;
+ let TSFlags{48-46} = EVEX_CD8V;
+ let TSFlags{49} = has3DNow0F0FOpcode;
+ let TSFlags{50} = hasMemOp4Prefix;
+ let TSFlags{51} = hasXOP_Prefix;
}
class PseudoI<dag oops, dag iops, list<dag> pattern>
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