[PATCH v3 04/11] [x86] Add OpSize16 to instructions that need it
Craig Topper
craig.topper at gmail.com
Sun Jan 5 05:39:57 PST 2014
If we approached this from another direction and inverted the normal OpSize
bit in 16-bit mode, how many instructions would break?
On Fri, Dec 20, 2013 at 8:58 AM, David Woodhouse <dwmw2 at infradead.org>wrote:
> From: David Woodhouse <David.Woodhouse at intel.com>
>
> This fixes the bulk of 16-bit output, and the corresponding test case
> x86-16.s now looks mostly like the x86-32.s test case that it was
> originally based on. A few irrelevant instructions have been dropped,
> and there are still some corner cases to be fixed in subsequent patches.
> ---
> lib/Target/X86/X86InstrArithmetic.td | 71 +++++----
> lib/Target/X86/X86InstrCMovSetCC.td | 5 +-
> lib/Target/X86/X86InstrCompiler.td | 18 +--
> lib/Target/X86/X86InstrControl.td | 26 ++--
> lib/Target/X86/X86InstrInfo.td | 149 ++++++++++--------
> lib/Target/X86/X86InstrShiftRotate.td | 103 +++++++------
> lib/Target/X86/X86InstrSystem.td | 105 +++++++------
> test/MC/X86/x86-16.s | 277
> ++++++++++++++++++++++++++++++++++
> 8 files changed, 537 insertions(+), 217 deletions(-)
>
> diff --git a/lib/Target/X86/X86InstrArithmetic.td
> b/lib/Target/X86/X86InstrArithmetic.td
> index b8d7f9a..18a6192 100644
> --- a/lib/Target/X86/X86InstrArithmetic.td
> +++ b/lib/Target/X86/X86InstrArithmetic.td
> @@ -24,7 +24,7 @@ def LEA32r : I<0x8D, MRMSrcMem,
> (outs GR32:$dst), (ins i32mem:$src),
> "lea{l}\t{$src|$dst}, {$dst|$src}",
> [(set GR32:$dst, lea32addr:$src)], IIC_LEA>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
>
> def LEA64_32r : I<0x8D, MRMSrcMem,
> (outs GR32:$dst), (ins lea64_32mem:$src),
> @@ -74,7 +74,7 @@ let Defs = [EAX,EDX,EFLAGS], Uses = [EAX],
> neverHasSideEffects = 1 in
> def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
> "mul{l}\t$src",
> [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX,
> GR32:$src))*/],
> - IIC_MUL32_REG>, Sched<[WriteIMul]>;
> + IIC_MUL32_REG>, OpSize16, Sched<[WriteIMul]>;
> // RAX,RDX = RAX*GR64
> let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
> def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
> @@ -100,7 +100,7 @@ def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
> let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
> def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
> "mul{l}\t$src",
> - [], IIC_MUL32_MEM>, SchedLoadReg<WriteIMulLd>;
> + [], IIC_MUL32_MEM>, OpSize16, SchedLoadReg<WriteIMulLd>;
> // RAX,RDX = RAX*[mem64]
> let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
> def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
> @@ -119,7 +119,7 @@ def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src),
> "imul{w}\t$src", [],
> // EAX,EDX = EAX*GR32
> let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
> def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src",
> [],
> - IIC_IMUL32_RR>, Sched<[WriteIMul]>;
> + IIC_IMUL32_RR>, OpSize16, Sched<[WriteIMul]>;
> // RAX,RDX = RAX*GR64
> let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
> def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src",
> [],
> @@ -138,7 +138,8 @@ def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
> // EAX,EDX = EAX*[mem32]
> let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
> def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
> - "imul{l}\t$src", [], IIC_IMUL32_MEM>,
> SchedLoadReg<WriteIMulLd>;
> + "imul{l}\t$src", [], IIC_IMUL32_MEM>, OpSize16,
> + SchedLoadReg<WriteIMulLd>;
> // RAX,RDX = RAX*[mem64]
> let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
> def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
> @@ -162,7 +163,7 @@ def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst),
> (ins GR32:$src1,GR32:$src2),
> "imul{l}\t{$src2, $dst|$dst, $src2}",
> [(set GR32:$dst, EFLAGS,
> (X86smul_flag GR32:$src1, GR32:$src2))],
> IIC_IMUL32_RR>,
> - TB;
> + TB, OpSize16;
> def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
> (ins GR64:$src1, GR64:$src2),
> "imul{q}\t{$src2, $dst|$dst, $src2}",
> @@ -186,7 +187,7 @@ def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
> [(set GR32:$dst, EFLAGS,
> (X86smul_flag GR32:$src1, (load addr:$src2)))],
> IIC_IMUL32_RM>,
> - TB;
> + TB, OpSize16;
> def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
> (ins GR64:$src1, i64mem:$src2),
> "imul{q}\t{$src2, $dst|$dst, $src2}",
> @@ -221,13 +222,13 @@ def IMUL32rri : Ii32<0x69, MRMSrcReg,
> // GR32 = GR32*I32
> "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> [(set GR32:$dst, EFLAGS,
> (X86smul_flag GR32:$src1, imm:$src2))],
> - IIC_IMUL32_RRI>;
> + IIC_IMUL32_RRI>, OpSize16;
> def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 =
> GR32*I8
> (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
> "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> [(set GR32:$dst, EFLAGS,
> (X86smul_flag GR32:$src1, i32immSExt8:$src2))],
> - IIC_IMUL32_RRI>;
> + IIC_IMUL32_RRI>, OpSize16;
> def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 =
> GR64*I32
> (outs GR64:$dst), (ins GR64:$src1,
> i64i32imm:$src2),
> "imul{q}\t{$src2, $src1, $dst|$dst, $src1,
> $src2}",
> @@ -263,14 +264,14 @@ def IMUL32rmi : Ii32<0x69, MRMSrcMem,
> // GR32 = [mem32]*I32
> "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> [(set GR32:$dst, EFLAGS,
> (X86smul_flag (load addr:$src1), imm:$src2))],
> - IIC_IMUL32_RMI>;
> + IIC_IMUL32_RMI>, OpSize16;
> def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 =
> [mem32]*I8
> (outs GR32:$dst), (ins i32mem:$src1, i32i8imm:
> $src2),
> "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> [(set GR32:$dst, EFLAGS,
> (X86smul_flag (load addr:$src1),
> i32immSExt8:$src2))],
> - IIC_IMUL32_RMI>;
> + IIC_IMUL32_RMI>, OpSize16;
> def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 =
> [mem64]*I32
> (outs GR64:$dst), (ins i64mem:$src1,
> i64i32imm:$src2),
> "imul{q}\t{$src2, $src1, $dst|$dst, $src1,
> $src2}",
> @@ -302,7 +303,7 @@ def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src),
> // DX:AX/r16 = AX,DX
> "div{w}\t$src", [], IIC_DIV16>, OpSize;
> let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
> def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 =
> EAX,EDX
> - "div{l}\t$src", [], IIC_DIV32>;
> + "div{l}\t$src", [], IIC_DIV32>, OpSize16;
> // RDX:RAX/r64 = RAX,RDX
> let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
> def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
> @@ -321,7 +322,7 @@ def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src),
> // DX:AX/[mem16] = AX,DX
> let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] =
> EAX,EDX
> def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
> "div{l}\t$src", [], IIC_DIV32>,
> - SchedLoadReg<WriteIDivLd>;
> + SchedLoadReg<WriteIDivLd>, OpSize16;
> // RDX:RAX/[mem64] = RAX,RDX
> let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
> def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
> @@ -339,7 +340,7 @@ def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src),
> // DX:AX/r16 = AX,DX
> "idiv{w}\t$src", [], IIC_IDIV16>, OpSize;
> let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
> def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 =
> EAX,EDX
> - "idiv{l}\t$src", [], IIC_IDIV32>;
> + "idiv{l}\t$src", [], IIC_IDIV32>, OpSize16;
> // RDX:RAX/r64 = RAX,RDX
> let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
> def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
> @@ -357,7 +358,7 @@ def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src),
> // DX:AX/[mem16] = AX,DX
> SchedLoadReg<WriteIDivLd>;
> let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] =
> EAX,EDX
> def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
> - "idiv{l}\t$src", [], IIC_IDIV32>,
> + "idiv{l}\t$src", [], IIC_IDIV32>, OpSize16,
> SchedLoadReg<WriteIDivLd>;
> let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] =
> RAX,RDX
> def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
> @@ -385,7 +386,7 @@ def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins
> GR16:$src1),
> def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
> "neg{l}\t$dst",
> [(set GR32:$dst, (ineg GR32:$src1)),
> - (implicit EFLAGS)], IIC_UNARY_REG>;
> + (implicit EFLAGS)], IIC_UNARY_REG>, OpSize16;
> def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
> "neg{q}\t$dst",
> [(set GR64:$dst, (ineg GR64:$src1)),
> (implicit EFLAGS)], IIC_UNARY_REG>;
> @@ -404,7 +405,7 @@ def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
> def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
> "neg{l}\t$dst",
> [(store (ineg (loadi32 addr:$dst)), addr:$dst),
> - (implicit EFLAGS)], IIC_UNARY_MEM>;
> + (implicit EFLAGS)], IIC_UNARY_MEM>, OpSize16;
> def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
> [(store (ineg (loadi64 addr:$dst)), addr:$dst),
> (implicit EFLAGS)], IIC_UNARY_MEM>;
> @@ -425,7 +426,7 @@ def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins
> GR16:$src1),
> [(set GR16:$dst, (not GR16:$src1))], IIC_UNARY_REG>,
> OpSize;
> def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
> "not{l}\t$dst",
> - [(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>;
> + [(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>,
> OpSize16;
> def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
> "not{q}\t$dst",
> [(set GR64:$dst, (not GR64:$src1))], IIC_UNARY_REG>;
> }
> @@ -441,7 +442,8 @@ def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
> OpSize;
> def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
> "not{l}\t$dst",
> - [(store (not (loadi32 addr:$dst)), addr:$dst)],
> IIC_UNARY_MEM>;
> + [(store (not (loadi32 addr:$dst)), addr:$dst)],
> IIC_UNARY_MEM>,
> + OpSize16;
> def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
> [(store (not (loadi64 addr:$dst)), addr:$dst)],
> IIC_UNARY_MEM>;
> } // SchedRW
> @@ -465,7 +467,7 @@ def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins
> GR32:$src1),
> "inc{l}\t$dst",
> [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
> IIC_UNARY_REG>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
> def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
> "inc{q}\t$dst",
> [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))],
> IIC_UNARY_REG>;
> @@ -503,13 +505,13 @@ def INC32_16r : I<0xFF, MRM0r, (outs GR16:$dst),
> (ins GR16:$src1),
> OpSize, Requires<[Not64BitMode]>;
> def INC32_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
> "inc{l}\t$dst", [], IIC_UNARY_REG>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
> def DEC32_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
> "dec{w}\t$dst", [], IIC_UNARY_REG>,
> OpSize, Requires<[Not64BitMode]>;
> def DEC32_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
> "dec{l}\t$dst", [], IIC_UNARY_REG>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
> } // isCodeGenOnly = 1, CodeSize = 2
>
> } // Constraints = "$src1 = $dst", SchedRW
> @@ -525,7 +527,7 @@ let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
> def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
> [(store (add (loadi32 addr:$dst), 1), addr:$dst),
> (implicit EFLAGS)], IIC_UNARY_MEM>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
> def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
> [(store (add (loadi64 addr:$dst), 1), addr:$dst),
> (implicit EFLAGS)], IIC_UNARY_MEM>;
> @@ -567,7 +569,7 @@ def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins
> GR32:$src1),
> "dec{l}\t$dst",
> [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
> IIC_UNARY_REG>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
> def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
> "dec{q}\t$dst",
> [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))],
> IIC_UNARY_REG>;
> @@ -586,7 +588,7 @@ let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
> def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
> [(store (add (loadi32 addr:$dst), -1), addr:$dst),
> (implicit EFLAGS)], IIC_UNARY_MEM>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
> def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
> [(store (add (loadi64 addr:$dst), -1), addr:$dst),
> (implicit EFLAGS)], IIC_UNARY_MEM>;
> @@ -600,7 +602,8 @@ class X86TypeInfo<ValueType vt, string instrsuffix,
> RegisterClass regclass,
> PatFrag loadnode, X86MemOperand memoperand, ImmType
> immkind,
> Operand immoperand, SDPatternOperator immoperator,
> Operand imm8operand, SDPatternOperator imm8operator,
> - bit hasOddOpcode, bit hasOpSizePrefix, bit
> hasREX_WPrefix> {
> + bit hasOddOpcode, bit hasOpSizePrefix, bit
> hasOpSize16Prefix,
> + bit hasREX_WPrefix> {
> /// VT - This is the value type itself.
> ValueType VT = vt;
>
> @@ -651,9 +654,14 @@ class X86TypeInfo<ValueType vt, string instrsuffix,
> RegisterClass regclass,
> bit HasOddOpcode = hasOddOpcode;
>
> /// HasOpSizePrefix - This bit is set to true if the instruction should
> have
> - /// the 0x66 operand size prefix. This is set for i16 types.
> + /// the 0x66 operand size prefix in 32-bit or 64-bit modes. This is
> set for
> + /// i16 types.
> bit HasOpSizePrefix = hasOpSizePrefix;
>
> + /// HasOpSizePrefix - This bit is set to true if the instruction should
> have
> + /// the 0x66 operand size prefix in 16-bit mode. This is set for i32
> types.
> + bit HasOpSize16Prefix = hasOpSize16Prefix;
> +
> /// HasREX_WPrefix - This bit is set to true if the instruction should
> have
> /// the 0x40 REX prefix. This is set for i64 types.
> bit HasREX_WPrefix = hasREX_WPrefix;
> @@ -664,16 +672,16 @@ def invalid_node : SDNode<"<<invalid_node>>",
> SDTIntLeaf,[],"<<invalid_node>>">;
>
> def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem ,
> Imm8 , i8imm , imm, i8imm ,
> invalid_node,
> - 0, 0, 0>;
> + 0, 0, 0, 0>;
> def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem,
> Imm16, i16imm, imm, i16i8imm,
> i16immSExt8,
> - 1, 1, 0>;
> + 1, 1, 0, 0>;
> def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem,
> Imm32, i32imm, imm, i32i8imm,
> i32immSExt8,
> - 1, 0, 0>;
> + 1, 0, 1, 0>;
> def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem,
> Imm32, i64i32imm, i64immSExt32, i64i8imm,
> i64immSExt8,
> - 1, 0, 1>;
> + 1, 0, 0, 1>;
>
> /// ITy - This instruction base class takes the type info for the
> instruction.
> /// Using this, it:
> @@ -694,6 +702,7 @@ class ITy<bits<8> opcode, Format f, X86TypeInfo
> typeinfo, dag outs, dag ins,
>
> // Infer instruction prefixes from type info.
> let hasOpSizePrefix = typeinfo.HasOpSizePrefix;
> + let hasOpSize16Prefix = typeinfo.HasOpSize16Prefix;
> let hasREX_WPrefix = typeinfo.HasREX_WPrefix;
> }
>
> diff --git a/lib/Target/X86/X86InstrCMovSetCC.td
> b/lib/Target/X86/X86InstrCMovSetCC.td
> index a967a4d..6ea9c0e 100644
> --- a/lib/Target/X86/X86InstrCMovSetCC.td
> +++ b/lib/Target/X86/X86InstrCMovSetCC.td
> @@ -28,7 +28,7 @@ multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf
> CondNode> {
> !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
> [(set GR32:$dst,
> (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],
> - IIC_CMOV32_RR>, TB;
> + IIC_CMOV32_RR>, TB, OpSize16;
> def NAME#64rr
> :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
> !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
> @@ -49,7 +49,8 @@ multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf
> CondNode> {
> : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1,
> i32mem:$src2),
> !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
> [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
> - CondNode, EFLAGS))], IIC_CMOV32_RM>,
> TB;
> + CondNode, EFLAGS))], IIC_CMOV32_RM>,
> + TB, OpSize16;
> def NAME#64rm
> :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1,
> i64mem:$src2),
> !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
> diff --git a/lib/Target/X86/X86InstrCompiler.td
> b/lib/Target/X86/X86InstrCompiler.td
> index 7bfcad0..6ba1099 100644
> --- a/lib/Target/X86/X86InstrCompiler.td
> +++ b/lib/Target/X86/X86InstrCompiler.td
> @@ -224,7 +224,7 @@ def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs),
> (ins),
> let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
> isCodeGenOnly = 1 in
> def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
> - [(set GR32:$dst, 0)], IIC_ALU_NONMEM>,
> Sched<[WriteZero]>;
> + [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, OpSize16,
> Sched<[WriteZero]>;
>
> // Other widths can also make use of the 32-bit xor, which may have a
> smaller
> // encoding and avoid partial register updates.
> @@ -324,7 +324,7 @@ def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins),
> "{rep;movsw|rep movsw}",
> [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
> Requires<[Not64BitMode]>;
> def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
> - [(X86rep_movs i32)], IIC_REP_MOVS>, REP,
> + [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize16,
> Requires<[Not64BitMode]>;
> }
>
> @@ -355,7 +355,7 @@ let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
> Requires<[Not64BitMode]>;
> let Uses = [EAX,ECX,EDI] in
> def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep
> stosd}",
> - [(X86rep_stos i32)], IIC_REP_STOS>, REP,
> + [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize16,
> Requires<[Not64BitMode]>;
> }
>
> @@ -625,7 +625,7 @@ def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5},
> RegOpc{4},
> MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
> !strconcat(mnemonic, "{l}\t",
> "{$src2, $dst|$dst, $src2}"),
> - [], IIC_ALU_NONMEM>, LOCK;
> + [], IIC_ALU_NONMEM>, OpSize16, LOCK;
> def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
> RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
> MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
> @@ -652,7 +652,7 @@ def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5},
> ImmOpc{4},
> ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
> !strconcat(mnemonic, "{l}\t",
> "{$src2, $dst|$dst, $src2}"),
> - [], IIC_ALU_MEM>, LOCK;
> + [], IIC_ALU_MEM>, OpSize16, LOCK;
>
> def NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
> ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
> @@ -672,7 +672,7 @@ def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6},
> ImmOpc8{5}, ImmOpc8{4},
> ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
> !strconcat(mnemonic, "{l}\t",
> "{$src2, $dst|$dst, $src2}"),
> - [], IIC_ALU_MEM>, LOCK;
> + [], IIC_ALU_MEM>, OpSize16, LOCK;
> def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
> ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
> ImmMod, (outs), (ins i64mem :$dst, i64i8imm
> :$src2),
> @@ -704,7 +704,7 @@ def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
> [], IIC_UNARY_MEM>, OpSize, LOCK;
> def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
> !strconcat(mnemonic, "{l}\t$dst"),
> - [], IIC_UNARY_MEM>, LOCK;
> + [], IIC_UNARY_MEM>, OpSize16, LOCK;
> def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
> !strconcat(mnemonic, "{q}\t$dst"),
> [], IIC_UNARY_MEM>, LOCK;
> @@ -740,7 +740,7 @@ let isCodeGenOnly = 1, SchedRW = [WriteALULd,
> WriteRMW] in {
> let Defs = [EAX, EFLAGS], Uses = [EAX] in
> def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
> !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
> - [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, LOCK;
> + [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize16,
> LOCK;
> let Defs = [RAX, EFLAGS], Uses = [RAX] in
> def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
> !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
> @@ -790,7 +790,7 @@ multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8>
> opc, string mnemonic,
> [(set
> GR32:$dst,
> (!cast<PatFrag>(frag # "_32") addr:$ptr,
> GR32:$val))],
> - itin>;
> + itin>, OpSize16;
> def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
> (ins GR64:$val, i64mem:$ptr),
> !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
> diff --git a/lib/Target/X86/X86InstrControl.td
> b/lib/Target/X86/X86InstrControl.td
> index 7d610e6..91f6123 100644
> --- a/lib/Target/X86/X86InstrControl.td
> +++ b/lib/Target/X86/X86InstrControl.td
> @@ -23,24 +23,24 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
> hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
> def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
> "ret",
> - [(X86retflag 0)], IIC_RET>;
> + [(X86retflag 0)], IIC_RET>, OpSize16;
> def RETW : I <0xC3, RawFrm, (outs), (ins),
> "ret{w}",
> [], IIC_RET>, OpSize;
> def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
> "ret\t$amt",
> - [(X86retflag timm:$amt)], IIC_RET_IMM>;
> + [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize16;
> def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
> "ret{w}\t$amt",
> [], IIC_RET_IMM>, OpSize;
> def LRETL : I <0xCB, RawFrm, (outs), (ins),
> - "{l}ret{l|f}", [], IIC_RET>;
> + "{l}ret{l|f}", [], IIC_RET>, OpSize16;
> def LRETW : I <0xCB, RawFrm, (outs), (ins),
> "{l}ret{w|f}", [], IIC_RET>, OpSize;
> def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
> "{l}ret{q|f}", [], IIC_RET>;
> def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
> - "{l}ret{l|f}\t$amt", [], IIC_RET>;
> + "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize16;
> def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
> "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize;
> }
> @@ -114,10 +114,10 @@ let isBranch = 1, isTerminator = 1, hasSideEffects =
> 0, SchedRW = [WriteJump] in
> let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1
> in {
> def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst),
> "jmp{l}\t{*}$dst",
> [(brind GR32:$dst)], IIC_JMP_REG>,
> Requires<[Not64BitMode]>,
> - Sched<[WriteJump]>;
> + OpSize16, Sched<[WriteJump]>;
> def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
> "jmp{l}\t{*}$dst",
> [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>,
> - Requires<[Not64BitMode]>, Sched<[WriteJumpLd]>;
> + Requires<[Not64BitMode]>, OpSize16,
> Sched<[WriteJumpLd]>;
>
> def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
> "jmp{q}\t{*}$dst",
> [(brind GR64:$dst)], IIC_JMP_REG>,
> Requires<[In64BitMode]>,
> @@ -133,7 +133,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1,
> isIndirectBranch = 1 in {
> def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
> (ins i32imm:$off, i16imm:$seg),
> "ljmp{l}\t{$seg, $off|$off, $seg}", [],
> - IIC_JMP_FAR_PTR>, Sched<[WriteJump]>;
> + IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
> def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
> "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
> Sched<[WriteJump]>;
> @@ -142,7 +142,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1,
> isIndirectBranch = 1 in {
> "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize,
> Sched<[WriteJumpLd]>;
> def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
> - "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
> + "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16,
> Sched<[WriteJumpLd]>;
> }
>
> @@ -165,14 +165,14 @@ let isCall = 1 in
> let Uses = [ESP] in {
> def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
> (outs), (ins i32imm_pcrel:$dst),
> - "call{l}\t$dst", [], IIC_CALL_RI>,
> + "call{l}\t$dst", [], IIC_CALL_RI>, OpSize16,
> Requires<[Not64BitMode]>, Sched<[WriteJump]>;
> def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
> "call{l}\t{*}$dst", [(X86call GR32:$dst)],
> IIC_CALL_RI>,
> - Requires<[Not64BitMode]>, Sched<[WriteJump]>;
> + OpSize16, Requires<[Not64BitMode]>,
> Sched<[WriteJump]>;
> def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
> "call{l}\t{*}$dst", [(X86call (loadi32
> addr:$dst))],
> - IIC_CALL_MEM>,
> + IIC_CALL_MEM>, OpSize16,
> Requires<[Not64BitMode,FavorMemIndirectCall]>,
> Sched<[WriteJumpLd]>;
>
> @@ -183,13 +183,13 @@ let isCall = 1 in
> def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
> (ins i32imm:$off, i16imm:$seg),
> "lcall{l}\t{$seg, $off|$off, $seg}", [],
> - IIC_CALL_FAR_PTR>, Sched<[WriteJump]>;
> + IIC_CALL_FAR_PTR>, OpSize16,
> Sched<[WriteJump]>;
>
> def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
> "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>,
> OpSize,
> Sched<[WriteJumpLd]>;
> def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
> - "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>,
> + "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>,
> OpSize16,
> Sched<[WriteJumpLd]>;
>
> // callw for 16 bit code for the assembler.
> diff --git a/lib/Target/X86/X86InstrInfo.td
> b/lib/Target/X86/X86InstrInfo.td
> index 4fee939..2a4c8f3 100644
> --- a/lib/Target/X86/X86InstrInfo.td
> +++ b/lib/Target/X86/X86InstrInfo.td
> @@ -885,47 +885,46 @@ let mayLoad = 1, SchedRW = [WriteLoad] in {
> def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg",
> [],
> IIC_POP_REG16>, OpSize;
> def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg",
> [],
> - IIC_POP_REG>;
> + IIC_POP_REG>, OpSize16;
> def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
> IIC_POP_REG>, OpSize;
> def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst",
> [],
> IIC_POP_MEM>, OpSize;
> def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
> - IIC_POP_REG>;
> + IIC_POP_REG>, OpSize16;
> def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst",
> [],
> - IIC_POP_MEM>;
> + IIC_POP_MEM>, OpSize16;
>
> def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
> OpSize;
> def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [],
> IIC_POP_FD>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
> } // mayLoad, SchedRW
>
> let mayStore = 1, SchedRW = [WriteStore] in {
> def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg),
> "push{w}\t$reg",[],
> IIC_PUSH_REG>, OpSize;
> def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg),
> "push{l}\t$reg",[],
> - IIC_PUSH_REG>;
> + IIC_PUSH_REG>, OpSize16;
> def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
> IIC_PUSH_REG>, OpSize;
> def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src),
> "push{w}\t$src",[],
> - IIC_PUSH_MEM>,
> - OpSize;
> + IIC_PUSH_MEM>, OpSize;
> def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
> - IIC_PUSH_REG>;
> + IIC_PUSH_REG>, OpSize16;
> def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src),
> "push{l}\t$src",[],
> - IIC_PUSH_MEM>;
> + IIC_PUSH_MEM>, OpSize16;
>
> def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
> - "push{l}\t$imm", [], IIC_PUSH_IMM>;
> + "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
> def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
> "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize;
> def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
> - "push{l}\t$imm", [], IIC_PUSH_IMM>;
> + "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
>
> def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
> OpSize;
> def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [],
> IIC_PUSH_F>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
>
> } // mayStore, SchedRW
> }
> @@ -969,12 +968,12 @@ def PUSHF64 : I<0x9C, RawFrm, (outs), (ins),
> "pushfq", [], IIC_PUSH_F>,
> let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
> mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
> def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", [], IIC_POP_A>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
> }
> let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
> mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
> def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", [], IIC_PUSH_A>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
> }
>
> let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
> @@ -982,7 +981,7 @@ let Constraints = "$src = $dst", SchedRW = [WriteALU]
> in {
> def BSWAP32r : I<0xC8, AddRegFrm,
> (outs GR32:$dst), (ins GR32:$src),
> "bswap{l}\t$dst",
> - [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, TB;
> + [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>,
> OpSize16, TB;
>
> def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
> "bswap{q}\t$dst",
> @@ -1002,12 +1001,12 @@ def BSF16rm : I<0xBC, MRMSrcMem, (outs
> GR16:$dst), (ins i16mem:$src),
> def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
> "bsf{l}\t{$src, $dst|$dst, $src}",
> [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
> - IIC_BIT_SCAN_REG>, TB,
> + IIC_BIT_SCAN_REG>, TB, OpSize16,
> Sched<[WriteShift]>;
> def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
> "bsf{l}\t{$src, $dst|$dst, $src}",
> [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
> - IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;
> + IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
> def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
> "bsf{q}\t{$src, $dst|$dst, $src}",
> [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
> @@ -1030,12 +1029,12 @@ def BSR16rm : I<0xBD, MRMSrcMem, (outs
> GR16:$dst), (ins i16mem:$src),
> def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
> "bsr{l}\t{$src, $dst|$dst, $src}",
> [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
> - IIC_BIT_SCAN_REG>, TB,
> + IIC_BIT_SCAN_REG>, TB, OpSize16,
> Sched<[WriteShift]>;
> def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
> "bsr{l}\t{$src, $dst|$dst, $src}",
> [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
> - IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;
> + IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
> def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
> "bsr{q}\t{$src, $dst|$dst, $src}",
> [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
> IIC_BIT_SCAN_REG>, TB,
> @@ -1051,7 +1050,7 @@ let SchedRW = [WriteMicrocoded] in {
> let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
> def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
> def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;
> -def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>;
> +def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>,
> OpSize16;
> def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;
> }
>
> @@ -1061,18 +1060,20 @@ def STOSB : I<0xAA, RawFrm, (outs), (ins),
> "stosb", [], IIC_STOS>;
> let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
> def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;
> let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
> -def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>;
> +def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>,
> OpSize16;
> let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
> def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;
>
> def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
> def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>,
> OpSize;
> -def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>;
> +def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>,
> + OpSize16;
> def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;
>
> def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
> def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>,
> OpSize;
> -def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>;
> +def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>,
> + OpSize16;
> def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
> } // SchedRW
>
> @@ -1086,7 +1087,7 @@ def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst),
> (ins GR8 :$src),
> def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
> "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
> def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
> - "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
> + "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
> def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
> "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
> }
> @@ -1100,7 +1101,7 @@ def MOV16ri : Ii16<0xB8, AddRegFrm, (outs
> GR16:$dst), (ins i16imm:$src),
> [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
> def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
> "mov{l}\t{$src, $dst|$dst, $src}",
> - [(set GR32:$dst, imm:$src)], IIC_MOV>;
> + [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize16;
> def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
> "movabs{q}\t{$src, $dst|$dst, $src}",
> [(set GR64:$dst, imm:$src)], IIC_MOV>;
> @@ -1119,7 +1120,7 @@ def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins
> i16mem:$dst, i16imm:$src),
> [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>,
> OpSize;
> def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
> "mov{l}\t{$src, $dst|$dst, $src}",
> - [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>;
> + [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>,
> OpSize16;
> def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst,
> i64i32imm:$src),
> "mov{q}\t{$src, $dst|$dst, $src}",
> [(store i64immSExt32:$src, addr:$dst)],
> IIC_MOV_MEM>;
> @@ -1139,7 +1140,7 @@ def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins
> offset16:$src),
> Requires<[Not64BitMode]>;
> def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
> "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
> }
> let mayStore = 1 in {
> def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
> @@ -1150,7 +1151,7 @@ def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs
> offset16:$dst), (ins),
> Requires<[Not64BitMode]>;
> def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
> "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
> }
> }
>
> @@ -1193,7 +1194,7 @@ def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst),
> (ins GR8:$src),
> def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
> "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>,
> OpSize;
> def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
> - "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
> + "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>,
> OpSize16;
> def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
> "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
> }
> @@ -1207,7 +1208,7 @@ def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst),
> (ins i16mem:$src),
> [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>,
> OpSize;
> def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
> "mov{l}\t{$src, $dst|$dst, $src}",
> - [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>;
> + [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>,
> OpSize16;
> def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
> "mov{q}\t{$src, $dst|$dst, $src}",
> [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
> @@ -1222,7 +1223,7 @@ def MOV16mr : I<0x89, MRMDestMem, (outs), (ins
> i16mem:$dst, GR16:$src),
> [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
> def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
> "mov{l}\t{$src, $dst|$dst, $src}",
> - [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>;
> + [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
> def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
> "mov{q}\t{$src, $dst|$dst, $src}",
> [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
> @@ -1272,7 +1273,8 @@ def BT16rr : I<0xA3, MRMDestReg, (outs), (ins
> GR16:$src1, GR16:$src2),
> OpSize, TB;
> def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
> "bt{l}\t{$src2, $src1|$src1, $src2}",
> - [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))],
> IIC_BT_RR>, TB;
> + [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
> + OpSize16, TB;
> def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
> "bt{q}\t{$src2, $src1|$src1, $src2}",
> [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))],
> IIC_BT_RR>, TB;
> @@ -1295,7 +1297,7 @@ let mayLoad = 1, hasSideEffects = 0, SchedRW =
> [WriteALULd] in {
> // [(X86bt (loadi32 addr:$src1), GR32:$src2),
> // (implicit EFLAGS)]
> [], IIC_BT_MR
> - >, TB, Requires<[FastBTMem]>;
> + >, OpSize16, TB, Requires<[FastBTMem]>;
> def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1,
> GR64:$src2),
> "bt{q}\t{$src2, $src1|$src1, $src2}",
> // [(X86bt (loadi64 addr:$src1), GR64:$src2),
> @@ -1312,7 +1314,7 @@ def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins
> GR16:$src1, i16i8imm:$src2),
> def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
> "bt{l}\t{$src2, $src1|$src1, $src2}",
> [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
> - IIC_BT_RI>, TB;
> + IIC_BT_RI>, OpSize16, TB;
> def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
> "bt{q}\t{$src2, $src1|$src1, $src2}",
> [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
> @@ -1330,7 +1332,7 @@ def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins
> i16mem:$src1, i16i8imm:$src2),
> def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
> "bt{l}\t{$src2, $src1|$src1, $src2}",
> [(set EFLAGS, (X86bt (loadi32 addr:$src1),
> i32immSExt8:$src2))
> - ], IIC_BT_MI>, TB;
> + ], IIC_BT_MI>, OpSize16, TB;
> def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1,
> i64i8imm:$src2),
> "bt{q}\t{$src2, $src1|$src1, $src2}",
> [(set EFLAGS, (X86bt (loadi64 addr:$src1),
> @@ -1343,7 +1345,8 @@ def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins
> GR16:$src1, GR16:$src2),
> "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
> OpSize, TB;
> def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
> - "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
> TB;
> + "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
> + OpSize16, TB;
> def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
> "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
> TB;
> } // SchedRW
> @@ -1353,7 +1356,8 @@ def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins
> i16mem:$src1, GR16:$src2),
> "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
> OpSize, TB;
> def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
> - "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
> TB;
> + "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
> + OpSize16, TB;
> def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
> "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
> TB;
> }
> @@ -1363,7 +1367,8 @@ def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins
> GR16:$src1, i16i8imm:$src2),
> "btc{w}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_RI>,
> OpSize, TB;
> def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
> - "btc{l}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_RI>, TB;
> + "btc{l}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_RI>,
> + OpSize16, TB;
> def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
> "btc{q}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_RI>, TB;
> } // SchedRW
> @@ -1373,7 +1378,8 @@ def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins
> i16mem:$src1, i16i8imm:$src2),
> "btc{w}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_MI>,
> OpSize, TB;
> def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1,
> i32i8imm:$src2),
> - "btc{l}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_MI>, TB;
> + "btc{l}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_MI>,
> + OpSize16, TB;
> def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1,
> i64i8imm:$src2),
> "btc{q}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_MI>, TB;
> }
> @@ -1383,7 +1389,8 @@ def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins
> GR16:$src1, GR16:$src2),
> "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
> OpSize, TB;
> def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
> - "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
> TB;
> + "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
> + OpSize16, TB;
> def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
> "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
> } // SchedRW
> @@ -1393,7 +1400,8 @@ def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins
> i16mem:$src1, GR16:$src2),
> "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
> OpSize, TB;
> def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
> - "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
> TB;
> + "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
> + OpSize16, TB;
> def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
> "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
> TB;
> }
> @@ -1403,7 +1411,8 @@ def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins
> GR16:$src1, i16i8imm:$src2),
> "btr{w}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_RI>,
> OpSize, TB;
> def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
> - "btr{l}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_RI>, TB;
> + "btr{l}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_RI>,
> + OpSize16, TB;
> def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
> "btr{q}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_RI>, TB;
> } // SchedRW
> @@ -1413,7 +1422,8 @@ def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins
> i16mem:$src1, i16i8imm:$src2),
> "btr{w}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_MI>,
> OpSize, TB;
> def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1,
> i32i8imm:$src2),
> - "btr{l}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_MI>, TB;
> + "btr{l}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_MI>,
> + OpSize16, TB;
> def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1,
> i64i8imm:$src2),
> "btr{q}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_MI>, TB;
> }
> @@ -1423,7 +1433,8 @@ def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins
> GR16:$src1, GR16:$src2),
> "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
> OpSize, TB;
> def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
> - "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
> TB;
> + "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
> + OpSize16, TB;
> def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
> "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
> TB;
> } // SchedRW
> @@ -1433,7 +1444,8 @@ def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins
> i16mem:$src1, GR16:$src2),
> "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
> OpSize, TB;
> def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
> - "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
> TB;
> + "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
> + OpSize16, TB;
> def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
> "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
> TB;
> }
> @@ -1443,7 +1455,8 @@ def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins
> GR16:$src1, i16i8imm:$src2),
> "bts{w}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_RI>,
> OpSize, TB;
> def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
> - "bts{l}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_RI>, TB;
> + "bts{l}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_RI>,
> + OpSize16, TB;
> def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
> "bts{q}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_RI>, TB;
> } // SchedRW
> @@ -1453,7 +1466,8 @@ def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins
> i16mem:$src1, i16i8imm:$src2),
> "bts{w}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_MI>,
> OpSize, TB;
> def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1,
> i32i8imm:$src2),
> - "bts{l}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_MI>, TB;
> + "bts{l}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_MI>,
> + OpSize16, TB;
> def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1,
> i64i8imm:$src2),
> "bts{q}\t{$src2, $src1|$src1, $src2}", [],
> IIC_BTX_MI>, TB;
> }
> @@ -1490,7 +1504,7 @@ multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc,
> string mnemonic, string frag,
> [(set
> GR32:$dst,
> (!cast<PatFrag>(frag # "_32") addr:$ptr,
> GR32:$val))],
> - itin>;
> + itin>, OpSize16;
> def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
> (ins GR64:$val, i64mem:$ptr),
> !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr,
> $val}"),
> @@ -1511,7 +1525,8 @@ def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst),
> (ins GR8:$val, GR8:$src),
> def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val,
> GR16:$src),
> "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
> OpSize;
> def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val,
> GR32:$src),
> - "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
> + "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
> + OpSize16;
> def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins
> GR64:$val,GR64:$src),
> "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
> }
> @@ -1521,7 +1536,7 @@ def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins
> GR16:$src),
> "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>,
> OpSize;
> def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
> "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
> // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP
> encoding.
> // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
> def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
> @@ -1538,7 +1553,8 @@ def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst),
> (ins GR16:$src),
> "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>,
> TB,
> OpSize;
> def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
> - "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>,
> TB;
> + "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>,
> TB,
> + OpSize16;
> def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
> "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>,
> TB;
> } // SchedRW
> @@ -1550,7 +1566,8 @@ def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins
> i16mem:$dst, GR16:$src),
> "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>,
> TB,
> OpSize;
> def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
> - "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>,
> TB;
> + "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>,
> TB,
> + OpSize16;
> def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
> "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>,
> TB;
>
> @@ -1565,7 +1582,7 @@ def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs
> GR16:$dst), (ins GR16:$src),
> IIC_CMPXCHG_REG>, TB, OpSize;
> def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
> "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
> - IIC_CMPXCHG_REG>, TB;
> + IIC_CMPXCHG_REG>, TB, OpSize16;
> def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
> "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
> IIC_CMPXCHG_REG>, TB;
> @@ -1581,7 +1598,7 @@ def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins
> i16mem:$dst, GR16:$src),
> IIC_CMPXCHG_MEM>, TB, OpSize;
> def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst,
> GR32:$src),
> "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
> - IIC_CMPXCHG_MEM>, TB;
> + IIC_CMPXCHG_MEM>, TB, OpSize16;
> def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst,
> GR64:$src),
> "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
> IIC_CMPXCHG_MEM>, TB;
> @@ -1621,14 +1638,14 @@ def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins),
> "repne", []>;
> let SchedRW = [WriteMicrocoded] in {
> def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;
> def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;
> -def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>;
> +def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>,
> OpSize16;
> def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;
> }
>
> let SchedRW = [WriteSystem] in {
> def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
> def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
> -def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>;
> +def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>,
> OpSize16;
> }
>
> // Flag instructions
> @@ -1686,7 +1703,7 @@ def BOUNDS16rm : I<0x62, MRMSrcMem, (outs
> GR16:$dst), (ins i16mem:$src),
> "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>,
> OpSize,
> Requires<[Not64BitMode]>;
> def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
> - "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>,
> + "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>,
> OpSize16,
> Requires<[Not64BitMode]>;
>
> // Adjust RPL Field of Segment Selector
> @@ -1710,7 +1727,7 @@ let Predicates = [HasMOVBE] in {
> def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
> "movbe{l}\t{$src, $dst|$dst, $src}",
> [(set GR32:$dst, (bswap (loadi32 addr:$src)))],
> IIC_MOVBE>,
> - T8;
> + OpSize16, T8;
> def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
> "movbe{q}\t{$src, $dst|$dst, $src}",
> [(set GR64:$dst, (bswap (loadi64 addr:$src)))],
> IIC_MOVBE>,
> @@ -1724,7 +1741,7 @@ let Predicates = [HasMOVBE] in {
> def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst,
> GR32:$src),
> "movbe{l}\t{$src, $dst|$dst, $src}",
> [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
> - T8;
> + OpSize16, T8;
> def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst,
> GR64:$src),
> "movbe{q}\t{$src, $dst|$dst, $src}",
> [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
> @@ -1741,7 +1758,7 @@ let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
> [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
> def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
> "rdrand{l}\t$dst",
> - [(set GR32:$dst, EFLAGS, (X86rdrand))]>, TB;
> + [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
> def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
> "rdrand{q}\t$dst",
> [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
> @@ -1756,7 +1773,7 @@ let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
> [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize, TB;
> def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
> "rdseed{l}\t$dst",
> - [(set GR32:$dst, EFLAGS, (X86rdseed))]>, TB;
> + [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
> def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
> "rdseed{q}\t$dst",
> [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
> @@ -1777,11 +1794,12 @@ let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
>
> def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
> "lzcnt{l}\t{$src, $dst|$dst, $src}",
> - [(set GR32:$dst, (ctlz GR32:$src)), (implicit
> EFLAGS)]>, XS;
> + [(set GR32:$dst, (ctlz GR32:$src)), (implicit
> EFLAGS)]>, XS,
> + OpSize16;
> def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
> "lzcnt{l}\t{$src, $dst|$dst, $src}",
> [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
> - (implicit EFLAGS)]>, XS;
> + (implicit EFLAGS)]>, XS, OpSize16;
>
> def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
> "lzcnt{q}\t{$src, $dst|$dst, $src}",
> @@ -1808,11 +1826,12 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in {
>
> def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
> "tzcnt{l}\t{$src, $dst|$dst, $src}",
> - [(set GR32:$dst, (cttz GR32:$src)), (implicit
> EFLAGS)]>, XS;
> + [(set GR32:$dst, (cttz GR32:$src)), (implicit
> EFLAGS)]>, XS,
> + OpSize16;
> def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
> "tzcnt{l}\t{$src, $dst|$dst, $src}",
> [(set GR32:$dst, (cttz (loadi32 addr:$src))),
> - (implicit EFLAGS)]>, XS;
> + (implicit EFLAGS)]>, XS, OpSize16;
>
> def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
> "tzcnt{q}\t{$src, $dst|$dst, $src}",
> diff --git a/lib/Target/X86/X86InstrShiftRotate.td
> b/lib/Target/X86/X86InstrShiftRotate.td
> index 1937770..3be1129 100644
> --- a/lib/Target/X86/X86InstrShiftRotate.td
> +++ b/lib/Target/X86/X86InstrShiftRotate.td
> @@ -25,7 +25,7 @@ def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins
> GR16:$src1),
> [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize;
> def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
> "shl{l}\t{%cl, $dst|$dst, cl}",
> - [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>;
> + [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>,
> OpSize16;
> def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
> "shl{q}\t{%cl, $dst|$dst, cl}",
> [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
> @@ -42,7 +42,8 @@ def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins
> GR16:$src1, i8imm:$src2),
> OpSize;
> def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1,
> i8imm:$src2),
> "shl{l}\t{$src2, $dst|$dst, $src2}",
> - [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))],
> IIC_SR>;
> + [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))],
> IIC_SR>,
> + OpSize16;
> def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
> (ins GR64:$src1, i8imm:$src2),
> "shl{q}\t{$src2, $dst|$dst, $src2}",
> @@ -57,7 +58,7 @@ def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins
> GR8:$src1),
> def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
> "shl{w}\t$dst", [], IIC_SR>, OpSize;
> def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
> - "shl{l}\t$dst", [], IIC_SR>;
> + "shl{l}\t$dst", [], IIC_SR>, OpSize16;
> def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
> "shl{q}\t$dst", [], IIC_SR>;
> } // hasSideEffects = 0
> @@ -78,7 +79,8 @@ def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
> OpSize;
> def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
> "shl{l}\t{%cl, $dst|$dst, cl}",
> - [(store (shl (loadi32 addr:$dst), CL), addr:$dst)],
> IIC_SR>;
> + [(store (shl (loadi32 addr:$dst), CL), addr:$dst)],
> IIC_SR>,
> + OpSize16;
> def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
> "shl{q}\t{%cl, $dst|$dst, cl}",
> [(store (shl (loadi64 addr:$dst), CL), addr:$dst)],
> IIC_SR>;
> @@ -95,7 +97,7 @@ def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins
> i16mem:$dst, i8imm:$src),
> def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
> "shl{l}\t{$src, $dst|$dst, $src}",
> [(store (shl (loadi32 addr:$dst), (i8 imm:$src)),
> addr:$dst)],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
> "shl{q}\t{$src, $dst|$dst, $src}",
> [(store (shl (loadi64 addr:$dst), (i8 imm:$src)),
> addr:$dst)],
> @@ -114,7 +116,7 @@ def SHL16m1 : I<0xD1, MRM4m, (outs), (ins
> i16mem:$dst),
> def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
> "shl{l}\t$dst",
> [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
> "shl{q}\t$dst",
> [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
> @@ -131,7 +133,7 @@ def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins
> GR16:$src1),
> [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize;
> def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
> "shr{l}\t{%cl, $dst|$dst, cl}",
> - [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>;
> + [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>,
> OpSize16;
> def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
> "shr{q}\t{%cl, $dst|$dst, cl}",
> [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
> @@ -147,7 +149,7 @@ def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins
> GR16:$src1, i8imm:$src2),
> def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1,
> i8imm:$src2),
> "shr{l}\t{$src2, $dst|$dst, $src2}",
> [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1,
> i8imm:$src2),
> "shr{q}\t{$src2, $dst|$dst, $src2}",
> [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))],
> IIC_SR>;
> @@ -161,7 +163,7 @@ def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins
> GR16:$src1),
> [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>,
> OpSize;
> def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
> "shr{l}\t$dst",
> - [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>;
> + [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>,
> OpSize16;
> def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
> "shr{q}\t$dst",
> [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
> @@ -179,7 +181,8 @@ def SHR16mCL : I<0xD3, MRM5m, (outs), (ins
> i16mem:$dst),
> OpSize;
> def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
> "shr{l}\t{%cl, $dst|$dst, cl}",
> - [(store (srl (loadi32 addr:$dst), CL), addr:$dst)],
> IIC_SR>;
> + [(store (srl (loadi32 addr:$dst), CL), addr:$dst)],
> IIC_SR>,
> + OpSize16;
> def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
> "shr{q}\t{%cl, $dst|$dst, cl}",
> [(store (srl (loadi64 addr:$dst), CL), addr:$dst)],
> IIC_SR>;
> @@ -196,7 +199,7 @@ def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins
> i16mem:$dst, i8imm:$src),
> def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
> "shr{l}\t{$src, $dst|$dst, $src}",
> [(store (srl (loadi32 addr:$dst), (i8 imm:$src)),
> addr:$dst)],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
> "shr{q}\t{$src, $dst|$dst, $src}",
> [(store (srl (loadi64 addr:$dst), (i8 imm:$src)),
> addr:$dst)],
> @@ -214,7 +217,7 @@ def SHR16m1 : I<0xD1, MRM5m, (outs), (ins
> i16mem:$dst),
> def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
> "shr{l}\t$dst",
> [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
> "shr{q}\t$dst",
> [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
> @@ -234,7 +237,7 @@ def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins
> GR16:$src1),
> def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
> "sar{l}\t{%cl, $dst|$dst, cl}",
> [(set GR32:$dst, (sra GR32:$src1, CL))],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
> "sar{q}\t{%cl, $dst|$dst, cl}",
> [(set GR64:$dst, (sra GR64:$src1, CL))],
> @@ -253,7 +256,7 @@ def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins
> GR16:$src1, i8imm:$src2),
> def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1,
> i8imm:$src2),
> "sar{l}\t{$src2, $dst|$dst, $src2}",
> [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
> (ins GR64:$src1, i8imm:$src2),
> "sar{q}\t{$src2, $dst|$dst, $src2}",
> @@ -272,7 +275,7 @@ def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins
> GR16:$src1),
> def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
> "sar{l}\t$dst",
> [(set GR32:$dst, (sra GR32:$src1, (i8 1)))],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
> "sar{q}\t$dst",
> [(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
> @@ -293,7 +296,7 @@ def SAR16mCL : I<0xD3, MRM7m, (outs), (ins
> i16mem:$dst),
> def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
> "sar{l}\t{%cl, $dst|$dst, cl}",
> [(store (sra (loadi32 addr:$dst), CL), addr:$dst)],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
> "sar{q}\t{%cl, $dst|$dst, cl}",
> [(store (sra (loadi64 addr:$dst), CL), addr:$dst)],
> @@ -311,7 +314,7 @@ def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins
> i16mem:$dst, i8imm:$src),
> def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
> "sar{l}\t{$src, $dst|$dst, $src}",
> [(store (sra (loadi32 addr:$dst), (i8 imm:$src)),
> addr:$dst)],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
> "sar{q}\t{$src, $dst|$dst, $src}",
> [(store (sra (loadi64 addr:$dst), (i8 imm:$src)),
> addr:$dst)],
> @@ -330,7 +333,7 @@ def SAR16m1 : I<0xD1, MRM7m, (outs), (ins
> i16mem:$dst),
> def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
> "sar{l}\t$dst",
> [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
> "sar{q}\t$dst",
> [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
> @@ -360,12 +363,12 @@ def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins
> GR16:$src1),
> "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
>
> def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
> - "rcl{l}\t$dst", [], IIC_SR>;
> + "rcl{l}\t$dst", [], IIC_SR>, OpSize16;
> def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1,
> i8imm:$cnt),
> - "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
> + "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>,
> OpSize16;
> let Uses = [CL] in
> def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
> - "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
> + "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
>
>
> def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
> @@ -394,12 +397,12 @@ def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins
> GR16:$src1),
> "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
>
> def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
> - "rcr{l}\t$dst", [], IIC_SR>;
> + "rcr{l}\t$dst", [], IIC_SR>, OpSize16;
> def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1,
> i8imm:$cnt),
> - "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
> + "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>,
> OpSize16;
> let Uses = [CL] in
> def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
> - "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
> + "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
>
> def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
> "rcr{q}\t$dst", [], IIC_SR>;
> @@ -421,9 +424,9 @@ def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
> def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
> "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
> def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
> - "rcl{l}\t$dst", [], IIC_SR>;
> + "rcl{l}\t$dst", [], IIC_SR>, OpSize16;
> def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
> - "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
> + "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>,
> OpSize16;
> def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
> "rcl{q}\t$dst", [], IIC_SR>;
> def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
> @@ -438,9 +441,9 @@ def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
> def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
> "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
> def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
> - "rcr{l}\t$dst", [], IIC_SR>;
> + "rcr{l}\t$dst", [], IIC_SR>, OpSize16;
> def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
> - "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
> + "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>,
> OpSize16;
> def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
> "rcr{q}\t$dst", [], IIC_SR>;
> def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
> @@ -452,7 +455,7 @@ def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
> def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
> "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
> def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
> - "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
> + "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
> def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
> "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
>
> @@ -461,7 +464,7 @@ def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
> def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
> "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
> def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
> - "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
> + "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
> def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
> "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
> }
> @@ -479,7 +482,7 @@ def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins
> GR16:$src1),
> [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>,
> OpSize;
> def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
> "rol{l}\t{%cl, $dst|$dst, cl}",
> - [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>;
> + [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>,
> OpSize16;
> def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
> "rol{q}\t{%cl, $dst|$dst, cl}",
> [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
> @@ -496,7 +499,7 @@ def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins
> GR16:$src1, i8imm:$src2),
> def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1,
> i8imm:$src2),
> "rol{l}\t{$src2, $dst|$dst, $src2}",
> [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
> (ins GR64:$src1, i8imm:$src2),
> "rol{q}\t{$src2, $dst|$dst, $src2}",
> @@ -515,7 +518,7 @@ def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins
> GR16:$src1),
> def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
> "rol{l}\t$dst",
> [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
> "rol{q}\t$dst",
> [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
> @@ -535,7 +538,7 @@ def ROL16mCL : I<0xD3, MRM0m, (outs), (ins
> i16mem:$dst),
> def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
> "rol{l}\t{%cl, $dst|$dst, cl}",
> [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
> "rol{q}\t{%cl, $dst|$dst, cl}",
> [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
> @@ -553,7 +556,7 @@ def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins
> i16mem:$dst, i8imm:$src1),
> def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1),
> "rol{l}\t{$src1, $dst|$dst, $src1}",
> [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)),
> addr:$dst)],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1),
> "rol{q}\t{$src1, $dst|$dst, $src1}",
> [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)),
> addr:$dst)],
> @@ -572,7 +575,7 @@ def ROL16m1 : I<0xD1, MRM0m, (outs), (ins
> i16mem:$dst),
> def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
> "rol{l}\t$dst",
> [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
> "rol{q}\t$dst",
> [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
> @@ -589,7 +592,7 @@ def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins
> GR16:$src1),
> [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>,
> OpSize;
> def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
> "ror{l}\t{%cl, $dst|$dst, cl}",
> - [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>;
> + [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>,
> OpSize16;
> def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
> "ror{q}\t{%cl, $dst|$dst, cl}",
> [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
> @@ -606,7 +609,7 @@ def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins
> GR16:$src1, i8imm:$src2),
> def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1,
> i8imm:$src2),
> "ror{l}\t{$src2, $dst|$dst, $src2}",
> [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
> (ins GR64:$src1, i8imm:$src2),
> "ror{q}\t{$src2, $dst|$dst, $src2}",
> @@ -625,7 +628,7 @@ def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins
> GR16:$src1),
> def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
> "ror{l}\t$dst",
> [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
> "ror{q}\t$dst",
> [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))],
> @@ -645,7 +648,7 @@ def ROR16mCL : I<0xD3, MRM1m, (outs), (ins
> i16mem:$dst),
> def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
> "ror{l}\t{%cl, $dst|$dst, cl}",
> [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
> "ror{q}\t{%cl, $dst|$dst, cl}",
> [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],
> @@ -663,7 +666,7 @@ def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins
> i16mem:$dst, i8imm:$src),
> def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
> "ror{l}\t{$src, $dst|$dst, $src}",
> [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)),
> addr:$dst)],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
> "ror{q}\t{$src, $dst|$dst, $src}",
> [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)),
> addr:$dst)],
> @@ -682,7 +685,7 @@ def ROR16m1 : I<0xD1, MRM1m, (outs), (ins
> i16mem:$dst),
> def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
> "ror{l}\t$dst",
> [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)],
> - IIC_SR>;
> + IIC_SR>, OpSize16;
> def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
> "ror{q}\t$dst",
> [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
> @@ -713,12 +716,12 @@ def SHLD32rrCL : I<0xA5, MRMDestReg, (outs
> GR32:$dst),
> (ins GR32:$src1, GR32:$src2),
> "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
> [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
> CL))],
> - IIC_SHD32_REG_CL>, TB;
> + IIC_SHD32_REG_CL>, TB, OpSize16;
> def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
> (ins GR32:$src1, GR32:$src2),
> "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
> [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
> CL))],
> - IIC_SHD32_REG_CL>, TB;
> + IIC_SHD32_REG_CL>, TB, OpSize16;
> def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
> (ins GR64:$src1, GR64:$src2),
> "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
> @@ -754,14 +757,14 @@ def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
> "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
> [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
> (i8 imm:$src3)))],
> IIC_SHD32_REG_IM>,
> - TB;
> + TB, OpSize16;
> def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
> (outs GR32:$dst),
> (ins GR32:$src1, GR32:$src2, i8imm:$src3),
> "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
> [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
> (i8 imm:$src3)))],
> IIC_SHD32_REG_IM>,
> - TB;
> + TB, OpSize16;
> def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
> (outs GR64:$dst),
> (ins GR64:$src1, GR64:$src2, i8imm:$src3),
> @@ -793,11 +796,11 @@ def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins
> i16mem:$dst, GR16:$src2),
> def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst,
> GR32:$src2),
> "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
> [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
> - addr:$dst)], IIC_SHD32_MEM_CL>, TB;
> + addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize16;
> def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst,
> GR32:$src2),
> "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
> [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
> - addr:$dst)], IIC_SHD32_MEM_CL>, TB;
> + addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize16;
>
> def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst,
> GR64:$src2),
> "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
> @@ -830,14 +833,14 @@ def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
> [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
> (i8 imm:$src3)), addr:$dst)],
> IIC_SHD32_MEM_IM>,
> - TB;
> + TB, OpSize16;
> def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
> (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
> "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
> [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
> (i8 imm:$src3)), addr:$dst)],
> IIC_SHD32_MEM_IM>,
> - TB;
> + TB, OpSize16;
>
> def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
> (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
> diff --git a/lib/Target/X86/X86InstrSystem.td
> b/lib/Target/X86/X86InstrSystem.td
> index 27f753d..90a51c8 100644
> --- a/lib/Target/X86/X86InstrSystem.td
> +++ b/lib/Target/X86/X86InstrSystem.td
> @@ -65,7 +65,8 @@ def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins),
> "sysexit{q}", []>, TB,
> Requires<[In64BitMode]>;
>
> def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>,
> OpSize;
> -def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>;
> +def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>,
> + OpSize16;
> def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,
> Requires<[In64BitMode]>;
> } // SchedRW
> @@ -83,7 +84,7 @@ def IN16rr : I<0xED, RawFrm, (outs), (ins),
> "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize;
> let Defs = [EAX], Uses = [DX] in
> def IN32rr : I<0xED, RawFrm, (outs), (ins),
> - "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>;
> + "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize16;
>
> let Defs = [AL] in
> def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
> @@ -93,7 +94,7 @@ def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
> "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize;
> let Defs = [EAX] in
> def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
> - "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>;
> + "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>,
> OpSize16;
>
> let Uses = [DX, AL] in
> def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
> @@ -103,7 +104,7 @@ def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
> "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize;
> let Uses = [DX, EAX] in
> def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
> - "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>;
> + "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize16;
>
> let Uses = [AL] in
> def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
> @@ -113,11 +114,11 @@ def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins
> i8imm:$port),
> "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>,
> OpSize;
> let Uses = [EAX] in
> def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
> - "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>;
> + "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>,
> OpSize16;
>
> def IN8 : I<0x6C, RawFrm, (outs), (ins), "ins{b}", [], IIC_INS>;
> def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>, OpSize;
> -def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", [], IIC_INS>;
> +def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", [], IIC_INS>,
> OpSize16;
> } // SchedRW
>
>
> //===----------------------------------------------------------------------===//
> @@ -169,28 +170,28 @@ let SchedRW = [WriteMove] in {
> def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins
> SEGMENT_REG:$src),
> "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>,
> OpSize;
> def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins
> SEGMENT_REG:$src),
> - "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
> + "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>,
> OpSize16;
> def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins
> SEGMENT_REG:$src),
> "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
>
> def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins
> SEGMENT_REG:$src),
> "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>,
> OpSize;
> def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins
> SEGMENT_REG:$src),
> - "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
> + "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>,
> OpSize16;
> def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins
> SEGMENT_REG:$src),
> "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
>
> def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
> "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>,
> OpSize;
> def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
> - "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
> + "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>,
> OpSize16;
> def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins
> GR64:$src),
> "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
>
> def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins
> i16mem:$src),
> "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>,
> OpSize;
> def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins
> i32mem:$src),
> - "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
> + "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>,
> OpSize16;
> def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins
> i64mem:$src),
> "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
> } // SchedRW
> @@ -208,9 +209,11 @@ def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst),
> (ins GR16:$src),
>
> // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
> def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
> - "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
> + "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
> + OpSize16;
> def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
> - "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
> + "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
> + OpSize16;
> // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
> def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
> "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
> @@ -222,9 +225,11 @@ def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
> (ins i16mem:$src),
> def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
> "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
> OpSize;
> def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
> - "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
> + "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
> + OpSize16;
> def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
> - "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
> + "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
> + OpSize16;
> def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
> "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
> def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
> @@ -236,7 +241,7 @@ def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr),
> "invlpg\t$addr",
> def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
> "str{w}\t$dst", [], IIC_STR>, TB, OpSize;
> def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
> - "str{l}\t$dst", [], IIC_STR>, TB;
> + "str{l}\t$dst", [], IIC_STR>, TB, OpSize16;
> def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
> "str{q}\t$dst", [], IIC_STR>, TB;
> def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
> @@ -248,35 +253,39 @@ def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
> "ltr{w}\t$src", [], IIC_LTR>, TB;
>
> def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
> - "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
> Requires<[Not64BitMode]>,
> - OpSize;
> + "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
> + OpSize, Requires<[Not64BitMode]>;
> def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
> - "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
> Requires<[Not64BitMode]>;
> + "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
> + OpSize16, Requires<[Not64BitMode]>;
> def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
> - "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
> Requires<[Not64BitMode]>,
> - OpSize;
> + "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
> + OpSize, Requires<[Not64BitMode]>;
> def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
> - "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
> Requires<[Not64BitMode]>;
> + "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
> + OpSize16, Requires<[Not64BitMode]>;
> def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
> - "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
> Requires<[Not64BitMode]>,
> - OpSize;
> + "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
> + OpSize, Requires<[Not64BitMode]>;
> def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
> - "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
> Requires<[Not64BitMode]>;
> + "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
> + OpSize16, Requires<[Not64BitMode]>;
> def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
> - "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
> Requires<[Not64BitMode]>,
> - OpSize;
> + "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
> + OpSize, Requires<[Not64BitMode]>;
> def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
> - "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
> Requires<[Not64BitMode]>;
> -
> + "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
> + OpSize16, Requires<[Not64BitMode]>;
> def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
> "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize, TB;
> def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
> - "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
> Requires<[Not64BitMode]>;
> + "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
> + OpSize16, Requires<[Not64BitMode]>;
> def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
> "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize, TB;
> def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
> - "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
> Requires<[Not64BitMode]>;
> -
> + "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
> + OpSize16, Requires<[Not64BitMode]>;
> def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
> "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB;
> def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
> @@ -288,33 +297,35 @@ def POPSS16 : I<0x17, RawFrm, (outs), (ins),
> OpSize, Requires<[Not64BitMode]>;
> def POPSS32 : I<0x17, RawFrm, (outs), (ins),
> "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
>
> def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
> "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
> OpSize, Requires<[Not64BitMode]>;
> def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
> "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
>
> def POPES16 : I<0x07, RawFrm, (outs), (ins),
> "pop{w}\t{%es|es}", [], IIC_POP_SR>,
> OpSize, Requires<[Not64BitMode]>;
> def POPES32 : I<0x07, RawFrm, (outs), (ins),
> "pop{l}\t{%es|es}", [], IIC_POP_SR>,
> - Requires<[Not64BitMode]>;
> + OpSize16, Requires<[Not64BitMode]>;
>
> def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
> "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize, TB;
> def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
> - "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
> Requires<[Not64BitMode]>;
> + "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
> + OpSize16, Requires<[Not64BitMode]>;
> def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
> "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB;
>
> def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
> "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize, TB;
> def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
> - "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
> Requires<[Not64BitMode]>;
> + "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
> + OpSize16, Requires<[Not64BitMode]>;
> def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
> "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB;
>
> @@ -322,31 +333,31 @@ def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
> def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
> "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
> def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
> - "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>;
> + "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
>
> def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
> "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB,
> OpSize;
> def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
> - "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
> + "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB,
> OpSize16;
> def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins
> opaque80mem:$src),
> "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
>
> def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
> "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
> def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
> - "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>;
> + "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
>
> def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
> "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB,
> OpSize;
> def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
> - "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
> + "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB,
> OpSize16;
> def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins
> opaque80mem:$src),
> "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
>
> def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
> "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB,
> OpSize;
> def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
> - "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
> + "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB,
> OpSize16;
>
> def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins
> opaque80mem:$src),
> "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
> @@ -369,17 +380,17 @@ let SchedRW = [WriteSystem] in {
> def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
> "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize,
> Requires<[Not64BitMode]>;
> def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
> - "sgdt\t$dst", [], IIC_SGDT>, TB;
> + "sgdt\t$dst", [], IIC_SGDT>, OpSize16, TB;
> def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
> "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize,
> Requires<[Not64BitMode]>;
> def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
> - "sidt\t$dst", []>, TB;
> + "sidt\t$dst", []>, OpSize16, TB;
> def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
> "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize;
> def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
> "sldt{w}\t$dst", [], IIC_SLDT>, TB;
> def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
> - "sldt{l}\t$dst", [], IIC_SLDT>, TB;
> + "sldt{l}\t$dst", [], IIC_SLDT>, OpSize16, TB;
>
> // LLDT is not interpreted specially in 64-bit mode because there is no
> sign
> // extension.
> @@ -391,11 +402,11 @@ def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst),
> (ins),
> def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
> "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize,
> Requires<[Not64BitMode]>;
> def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
> - "lgdt\t$src", [], IIC_LGDT>, TB;
> + "lgdt\t$src", [], IIC_LGDT>, OpSize16, TB;
> def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
> "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize,
> Requires<[Not64BitMode]>;
> def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
> - "lidt\t$src", [], IIC_LIDT>, TB;
> + "lidt\t$src", [], IIC_LIDT>, OpSize16, TB;
> def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
> "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
> def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
> @@ -412,7 +423,7 @@ def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc",
> [], IIC_RDPMC>, TB;
> def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
> "smsw{w}\t$dst", [], IIC_SMSW>, OpSize, TB;
> def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
> - "smsw{l}\t$dst", [], IIC_SMSW>, TB;
> + "smsw{l}\t$dst", [], IIC_SMSW>, OpSize16, TB;
> // no m form encodable; use SMSW16m
> def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
> "smsw{q}\t$dst", [], IIC_SMSW>, TB;
> diff --git a/test/MC/X86/x86-16.s b/test/MC/X86/x86-16.s
> index 115132d..d160d46 100644
> --- a/test/MC/X86/x86-16.s
> +++ b/test/MC/X86/x86-16.s
> @@ -2,6 +2,9 @@
>
> .code16
>
> + movl $0x12345678, %ebx
> +// CHECK: movl
> +// CHECK: encoding: [0x66,0xbb,0x78,0x56,0x34,0x12]
> pause
> // CHECK: pause
> // CHECK: encoding: [0xf3,0x90]
> @@ -24,12 +27,28 @@
> // CHECK: encoding: [0x0f,0x01,0xf9]
>
>
> +// CHECK: movl %eax, 16(%ebp) # encoding:
> [0x67,0x66,0x89,0x45,0x10]
> + movl %eax, 16(%ebp)
> +// CHECK: movl %eax, -16(%ebp) # encoding:
> [0x67,0x66,0x89,0x45,0xf0]
> + movl %eax, -16(%ebp)
> +
> // CHECK: testb %bl, %cl # encoding: [0x84,0xcb]
> testb %bl, %cl
>
> +// CHECK: cmpl %eax, %ebx # encoding: [0x66,0x39,0xc3]
> + cmpl %eax, %ebx
> +
> // CHECK: addw %ax, %ax # encoding: [0x01,0xc0]
> addw %ax, %ax
>
> +// CHECK: shrl %eax # encoding: [0x66,0xd1,0xe8]
> + shrl $1, %eax
> +
> +// CHECK: shll %eax # encoding: [0x66,0xd1,0xe0]
> + sall $1, %eax
> +// CHECK: shll %eax # encoding: [0x66,0xd1,0xe0]
> + sal $1, %eax
> +
> into
> // CHECK: into
> // CHECK: encoding: [0xce]
> @@ -43,10 +62,143 @@ int $255
> // CHECK: int $255
> // CHECK: encoding: [0xcd,0xff]
>
> +// CHECK: pushfl # encoding: [0x66,0x9c]
> + pushfl
> +// CHECK: popfl # encoding: [0x66,0x9d]
> + popfl
> +
> +// CHECK: cmoval %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x47,0xd0]
> + cmoval %eax,%edx
> +
> +// CHECK: cmovael %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x43,0xd0]
> + cmovael %eax,%edx
> +
> +// CHECK: cmovbel %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x46,0xd0]
> + cmovbel %eax,%edx
> +
> +// CHECK: cmovbl %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x42,0xd0]
> + cmovbl %eax,%edx
> +
> // CHECK: cmovbw %bx, %bx
> cmovnae %bx,%bx
>
>
> +// CHECK: cmovbel %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x46,0xd0]
> + cmovbel %eax,%edx
> +
> +// CHECK: cmovbl %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x42,0xd0]
> + cmovcl %eax,%edx
> +
> +// CHECK: cmovel %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x44,0xd0]
> + cmovel %eax,%edx
> +
> +// CHECK: cmovgl %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x4f,0xd0]
> + cmovgl %eax,%edx
> +
> +// CHECK: cmovgel %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x4d,0xd0]
> + cmovgel %eax,%edx
> +
> +// CHECK: cmovll %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x4c,0xd0]
> + cmovll %eax,%edx
> +
> +// CHECK: cmovlel %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x4e,0xd0]
> + cmovlel %eax,%edx
> +
> +// CHECK: cmovbel %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x46,0xd0]
> + cmovnal %eax,%edx
> +
> +// CHECK: cmovnel %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x45,0xd0]
> + cmovnel %eax,%edx
> +
> +// CHECK: cmovael %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x43,0xd0]
> + cmovnbl %eax,%edx
> +
> +// CHECK: cmoval %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x47,0xd0]
> + cmovnbel %eax,%edx
> +
> +// CHECK: cmovael %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x43,0xd0]
> + cmovncl %eax,%edx
> +
> +// CHECK: cmovnel %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x45,0xd0]
> + cmovnel %eax,%edx
> +
> +// CHECK: cmovlel %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x4e,0xd0]
> + cmovngl %eax,%edx
> +
> +// CHECK: cmovgel %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x4d,0xd0]
> + cmovnl %eax,%edx
> +
> +// CHECK: cmovnel %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x45,0xd0]
> + cmovnel %eax,%edx
> +
> +// CHECK: cmovlel %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x4e,0xd0]
> + cmovngl %eax,%edx
> +
> +// CHECK: cmovll %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x4c,0xd0]
> + cmovngel %eax,%edx
> +
> +// CHECK: cmovgel %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x4d,0xd0]
> + cmovnll %eax,%edx
> +
> +// CHECK: cmovgl %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x4f,0xd0]
> + cmovnlel %eax,%edx
> +
> +// CHECK: cmovnol %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x41,0xd0]
> + cmovnol %eax,%edx
> +
> +// CHECK: cmovnpl %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x4b,0xd0]
> + cmovnpl %eax,%edx
> +
> +// CHECK: cmovnsl %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x49,0xd0]
> + cmovnsl %eax,%edx
> +
> +// CHECK: cmovnel %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x45,0xd0]
> + cmovnzl %eax,%edx
> +
> +// CHECK: cmovol %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x40,0xd0]
> + cmovol %eax,%edx
> +
> +// CHECK: cmovpl %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x4a,0xd0]
> + cmovpl %eax,%edx
> +
> +// CHECK: cmovsl %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x48,0xd0]
> + cmovsl %eax,%edx
> +
> +// CHECK: cmovel %eax, %edx
> +// CHECK: encoding: [0x66,0x0f,0x44,0xd0]
> + cmovzl %eax,%edx
> +
> // CHECK: fmul %st(0)
> // CHECK: encoding: [0xd8,0xc8]
> fmul %st(0), %st
> @@ -71,14 +223,30 @@ cmovnae %bx,%bx
> // CHECK: encoding: [0xd8,0xf0]
> fdiv %st(0), %st
>
> +// CHECK: movl %cs, %eax
> +// CHECK: encoding: [0x66,0x8c,0xc8]
> + movl %cs, %eax
> +
> // CHECK: movw %cs, %ax
> // CHECK: encoding: [0x8c,0xc8]
> movw %cs, %ax
>
> +// CHECK: movl %cs, (%eax)
> +// CHECK: encoding: [0x67,0x66,0x8c,0x08]
> + movl %cs, (%eax)
> +
> // CHECK: movw %cs, (%eax)
> // CHECK: encoding: [0x67,0x8c,0x08]
> movw %cs, (%eax)
>
> +// CHECK: movl %eax, %cs
> +// CHECK: encoding: [0x66,0x8e,0xc8]
> + movl %eax, %cs
> +
> +// CHECK: movl (%eax), %cs
> +// CHECK: encoding: [0x67,0x66,0x8e,0x08]
> + movl (%eax), %cs
> +
> // CHECK: movw (%eax), %cs
> // CHECK: encoding: [0x67,0x8e,0x08]
> movw (%eax), %cs
> @@ -143,6 +311,23 @@ cmovnae %bx,%bx
> // CHECK: encoding: [0x9b]
> fwait
>
> +// CHECK: pushal
> +// CHECK: encoding: [0x66,0x60]
> + pushal
> +
> +// CHECK: popal
> +// CHECK: encoding: [0x66,0x61]
> + popal
> +
> +// CHECK: jmpl *8(%eax)
> +// CHECK: encoding: [0x67,0x66,0xff,0x60,0x08]
> + jmpl *8(%eax)
> +
> +// CHECK: lcalll $2, $4660
> +// CHECK: encoding: [0x66,0x9a,0x34,0x12,0x00,0x00,0x02,0x00]
> +lcalll $0x2, $0x1234
> +
> +
> sysret
> // CHECK: sysretl
> // CHECK: encoding: [0x0f,0x07]
> @@ -175,6 +360,35 @@ pushw %gs
> // CHECK: pushw %gs
> // CHECK: encoding: [0x0f,0xa8]
>
> +pushl %cs
> +// CHECK: pushl %cs
> +// CHECK: encoding: [0x66,0x0e]
> +pushl %ds
> +// CHECK: pushl %ds
> +// CHECK: encoding: [0x66,0x1e]
> +pushl %ss
> +// CHECK: pushl %ss
> +// CHECK: encoding: [0x66,0x16]
> +pushl %es
> +// CHECK: pushl %es
> +// CHECK: encoding: [0x66,0x06]
> +pushl %fs
> +// CHECK: pushl %fs
> +// CHECK: encoding: [0x66,0x0f,0xa0]
> +pushl %gs
> +// CHECK: pushl %gs
> +// CHECK: encoding: [0x66,0x0f,0xa8]
> +
> +popl %ss
> +// CHECK: popl %ss
> +// CHECK: encoding: [0x66,0x17]
> +popl %ds
> +// CHECK: popl %ds
> +// CHECK: encoding: [0x66,0x1f]
> +popl %es
> +// CHECK: popl %es
> +// CHECK: encoding: [0x66,0x07]
> +
> pushfd
> // CHECK: pushfl
> popfd
> @@ -222,12 +436,18 @@ ljmpl $0x7ace,$0x7ace
> // CHECK: incw %ax # encoding: [0x40]
> incw %ax
>
> +// CHECK: incl %eax # encoding: [0x66,0x40]
> + incl %eax
> +
> // CHECK: decb %al # encoding: [0xfe,0xc8]
> decb %al
>
> // CHECK: decw %ax # encoding: [0x48]
> decw %ax
>
> +// CHECK: decl %eax # encoding: [0x66,0x48]
> + decl %eax
> +
> // CHECK: pshufw $14, %mm4, %mm0 # encoding: [0x0f,0x70,0xc4,0x0e]
> pshufw $14, %mm4, %mm0
>
> @@ -278,6 +498,10 @@ pshufw $90, %mm4, %mm0
> // CHECK: encoding: [0x67,0x62,0x58,0x02]
> bound 2(%eax),%bx
>
> +// CHECK: bound 4(%ebx), %ecx
> +// CHECK: encoding: [0x67,0x66,0x62,0x4b,0x04]
> + bound 4(%ebx),%ecx
> +
> // CHECK: arpl %bx, %bx
> // CHECK: encoding: [0x63,0xdb]
> arpl %bx,%bx
> @@ -352,6 +576,12 @@ pshufw $90, %mm4, %mm0
> outsw %ds:(%si), %dx
> outsw (%si), %dx
>
> +// CHECK: outsl # encoding: [0x66,0x6f]
> +// CHECK: outsl
> + outsl
> + outsl %ds:(%si), %dx
> + outsl (%si), %dx
> +
> // CHECK: insb # encoding: [0x6c]
> // CHECK: insb
> insb
> @@ -362,6 +592,11 @@ pshufw $90, %mm4, %mm0
> insw
> insw %dx, %es:(%di)
>
> +// CHECK: insl # encoding: [0x66,0x6d]
> +// CHECK: insl
> + insl
> + insl %dx, %es:(%di)
> +
> // CHECK: movsb # encoding: [0xa4]
> // CHECK: movsb
> // CHECK: movsb
> @@ -376,6 +611,13 @@ pshufw $90, %mm4, %mm0
> movsw %ds:(%si), %es:(%di)
> movsw (%si), %es:(%di)
>
> +// CHECK: movsl # encoding: [0x66,0xa5]
> +// CHECK: movsl
> +// CHECK: movsl
> + movsl
> + movsl %ds:(%si), %es:(%di)
> + movsl (%si), %es:(%di)
> +
> // CHECK: lodsb # encoding: [0xac]
> // CHECK: lodsb
> // CHECK: lodsb
> @@ -398,6 +640,17 @@ pshufw $90, %mm4, %mm0
> lods %ds:(%si), %ax
> lods (%si), %ax
>
> +// CHECK: lodsl # encoding: [0x66,0xad]
> +// CHECK: lodsl
> +// CHECK: lodsl
> +// CHECK: lodsl
> +// CHECK: lodsl
> + lodsl
> + lodsl %ds:(%si), %eax
> + lodsl (%si), %eax
> + lods %ds:(%si), %eax
> + lods (%si), %eax
> +
> // CHECK: stosb # encoding: [0xaa]
> // CHECK: stosb
> // CHECK: stosb
> @@ -412,10 +665,22 @@ pshufw $90, %mm4, %mm0
> stosw %ax, %es:(%di)
> stos %ax, %es:(%di)
>
> +// CHECK: stosl # encoding: [0x66,0xab]
> +// CHECK: stosl
> +// CHECK: stosl
> + stosl
> + stosl %eax, %es:(%di)
> + stos %eax, %es:(%di)
> +
> // CHECK: strw
> // CHECK: encoding: [0x0f,0x00,0xc8]
> str %ax
>
> +// CHECK: strl
> +// CHECK: encoding: [0x66,0x0f,0x00,0xc8]
> + str %eax
> +
> +
> // CHECK: fsubp
> // CHECK: encoding: [0xde,0xe1]
> fsubp %st,%st(1)
> @@ -424,6 +689,18 @@ fsubp %st,%st(1)
> // CHECK: encoding: [0xde,0xe2]
> fsubp %st, %st(2)
>
> +// CHECK: xchgl %eax, %eax
> +// CHECK: encoding: [0x66,0x90]
> +xchgl %eax, %eax
> +
> // CHECK: xchgw %ax, %ax
> // CHECK: encoding: [0x90]
> xchgw %ax, %ax
> +
> +// CHECK: xchgl %ecx, %eax
> +// CHECK: encoding: [0x66,0x91]
> +xchgl %ecx, %eax
> +
> +// CHECK: xchgl %ecx, %eax
> +// CHECK: encoding: [0x66,0x91]
> +xchgl %eax, %ecx
> --
> 1.8.3.1
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
--
~Craig
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