[llvm] r198174 - ARM IAS: fix after r198172

[Saleem Abdulrasool]

Author: compnerd
Date: Sun Dec 29 12:53:16 2013
New Revision: 198174

URL: http://llvm.org/viewvc/llvm-project?rev=198174&view=rev
Log:
ARM IAS: fix after r198172

The DPR and SPR register lists are also register lists.  Furthermore, the
registers need not be checked individually since the register type can be
checked via the list kind.  Use that to simplify the logic and fix the incorrect
assertion.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=198174&r1=198173&r2=198174&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sun Dec 29 12:53:16 2013
@@ -5112,13 +5112,13 @@ bool ARMAsmParser::ParseInstruction(Pars
                                     SMLoc NameLoc,
                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
   // FIXME: Can this be done via tablegen in some fashion?
-  bool HasPrecisionRestrictions;
+  bool RequireVFPRegisterList;
   bool AcceptDoublePrecisionOnly;
   bool AcceptSinglePrecisionOnly;
-  HasPrecisionRestrictions = Name.startswith("fldm") || Name.startswith("fstm");
+  RequireVFPRegisterList = Name.startswith("fldm") || Name.startswith("fstm");
   AcceptDoublePrecisionOnly =
-    HasPrecisionRestrictions && (Name.back() == 'd' || Name.back() == 'x');
-  AcceptSinglePrecisionOnly = HasPrecisionRestrictions && Name.back() == 's';
+    RequireVFPRegisterList && (Name.back() == 'd' || Name.back() == 'x');
+  AcceptSinglePrecisionOnly = RequireVFPRegisterList && Name.back() == 's';
 
   // Apply mnemonic aliases before doing anything else, as the destination
   // mnemonic may include suffices and we want to handle them normally.
@@ -5288,24 +5288,14 @@ bool ARMAsmParser::ParseInstruction(Pars
 
   Parser.Lex(); // Consume the EndOfStatement
 
-  if (HasPrecisionRestrictions) {
+  if (RequireVFPRegisterList) {
     ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());
-    assert(Op->isRegList());
-    const SmallVectorImpl<unsigned> &RegList = Op->getRegList();
-    for (SmallVectorImpl<unsigned>::const_iterator RLI = RegList.begin(),
-                                                   RLE = RegList.end();
-         RLI != RLE; ++RLI) {
-      if (AcceptSinglePrecisionOnly &&
-          !ARMMCRegisterClasses[ARM::SPRRegClassID].contains(*RLI))
-        return Error(Op->getStartLoc(),
-                     "VFP/Neon single precision register expected");
-      else if (AcceptDoublePrecisionOnly &&
-               !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(*RLI))
-        return Error(Op->getStartLoc(),
-                     "VFP/Neon double precision register expected");
-      else
-        llvm_unreachable("must have single or double precision restrictions");
-    }
+    if (AcceptSinglePrecisionOnly && !Op->isSPRRegList())
+      return Error(Op->getStartLoc(),
+                   "VFP/Neon single precision register expected");
+    if (AcceptDoublePrecisionOnly && !Op->isDPRRegList())
+      return Error(Op->getStartLoc(),
+                   "VFP/Neon double precision register expected");
   }
 
   // Some instructions, mostly Thumb, have forms for the same mnemonic that