[PATCH] [AArch64] Add register spill code for large super registers such as DPair, DTriple ...

[Jiangning Liu]

  Hao,

  The fix logic should be OK for me to upstream, but I have two comments for the patch,

  1) Some code needs to be further refactored as described.
  2) The example can be further simplified as I give. Also, I think it would be better to cover all vector list types with 6 test cases.

  Besides, the test case itself is simple enough, and we don't really have high register pressure here, so we shouldn't introduce any spill/fill code. We need further fix to avoid spill/fill at all.

  Thanks,
  -Jiangning


================
Comment at: lib/Target/AArch64/AArch64InstrInfo.cpp:421
@@ -420,3 +420,3 @@
     }
-  } else {
+  } else if (RC->getSize() <= 16 && RC != &AArch64::DPairRegClass) {
     assert((RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
----------------
Can this line be replaced with

} else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) || RC->hasType(MVT::f128)) {

================
Comment at: lib/Target/AArch64/AArch64InstrInfo.cpp:422
@@ -422,2 +421,3 @@
+  } else if (RC->getSize() <= 16 && RC != &AArch64::DPairRegClass) {
     assert((RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
             RC->hasType(MVT::f128))
----------------
This assert can be removed.

================
Comment at: lib/Target/AArch64/AArch64RegisterInfo.cpp:151
@@ -133,1 +150,3 @@
     TII.getAddressConstraints(MI, OffsetScale, MinOffset, MaxOffset);
+  } else {
+    // As a vector load/store can't has an offset operand. If the offset is not
----------------
Remove this "else" construct and combine it with the following block like,

// We have to use additional add instruction for the following two scenarios
// 1) Offset can't really be scaled
// 2) Instruction can't encode Offset
  if (Offset % OffsetScale != 0 || Offset < MinOffset || Offset > MaxOffset) {
     || (!hasOffsetOp && (Offset != 0)) {
    unsigned BaseReg =
      MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
    emitRegUpdate(MBB, MBBI, MBBI->getDebugLoc(), TII,
                  BaseReg, FrameReg, BaseReg, Offset);
    FrameReg = BaseReg;
    Offset = 0;
  }


================
Comment at: test/CodeGen/AArch64/neon-vector-list-spill.ll:3
@@ +2,3 @@
+
+define i32 @spill.DPairReg(float* readonly %arg1, float %exp0, float %exp1) {
+entry:
----------------
This example can be simplified to be

declare { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2.v2i32(i8*, i32)
declare void @foo()

define i32 @spill.DPairReg(i8* %arg1, i32 %arg2) {
entry:
  %vld2 = tail call { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2.v2i32(i8* %arg1, i32 4)
  %cmp = icmp eq i32 %arg2, 0
  br i1 %cmp, label %if.then, label %if.end

if.then:
  tail call void @foo()
  br label %if.end

if.end:
  %vld2.extract = extractvalue { <2 x i32>, <2 x i32> } %vld2, 0
  %res = extractelement <2 x i32> %vld2.extract, i32 1
  ret i32 %res
}


http://llvm-reviews.chandlerc.com/D2438