[llvm] r197081 - Merge all tls tests to two files. One for normal codegen (initial and local
Roman Divacky
rdivacky at freebsd.org
Wed Dec 11 14:25:39 PST 2013
Author: rdivacky
Date: Wed Dec 11 16:25:39 2013
New Revision: 197081
URL: http://llvm.org/viewvc/llvm-project?rev=197081&view=rev
Log:
Merge all tls tests to two files. One for normal codegen (initial and local
exec) and one for PIC codegen (local and general dynamic).
Added:
llvm/trunk/test/CodeGen/PowerPC/tls-pic.ll
- copied, changed from r197072, llvm/trunk/test/CodeGen/PowerPC/tls-ld.ll
Removed:
llvm/trunk/test/CodeGen/PowerPC/tls-gd.ll
llvm/trunk/test/CodeGen/PowerPC/tls-ie.ll
llvm/trunk/test/CodeGen/PowerPC/tls-ld-2.ll
llvm/trunk/test/CodeGen/PowerPC/tls-ld.ll
Modified:
llvm/trunk/test/CodeGen/PowerPC/tls.ll
Removed: llvm/trunk/test/CodeGen/PowerPC/tls-gd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls-gd.ll?rev=197080&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls-gd.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls-gd.ll (removed)
@@ -1,23 +0,0 @@
-; RUN: llc -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck %s
-
-; Test correct assembly code generation for thread-local storage using
-; the general dynamic model.
-
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
- at a = thread_local global i32 0, align 4
-
-define signext i32 @main() nounwind {
-entry:
- %retval = alloca i32, align 4
- store i32 0, i32* %retval
- %0 = load i32* @a, align 4
- ret i32 %0
-}
-
-; CHECK: addis [[REG:[0-9]+]], 2, a at got@tlsgd at ha
-; CHECK-NEXT: addi 3, [[REG]], a at got@tlsgd at l
-; CHECK: bl __tls_get_addr(a at tlsgd)
-; CHECK-NEXT: nop
-
Removed: llvm/trunk/test/CodeGen/PowerPC/tls-ie.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls-ie.ll?rev=197080&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls-ie.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls-ie.ll (removed)
@@ -1,22 +0,0 @@
-; RUN: llc -mcpu=pwr7 -O0 <%s | FileCheck %s
-
-; Test correct assembly code generation for thread-local storage
-; using the initial-exec model.
-
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
- at a = external thread_local global i32
-
-define signext i32 @main() nounwind {
-entry:
- %retval = alloca i32, align 4
- store i32 0, i32* %retval
- %0 = load i32* @a, align 4
- ret i32 %0
-}
-
-; CHECK: addis [[REG1:[0-9]+]], 2, a at got@tprel at ha
-; CHECK: ld [[REG2:[0-9]+]], a at got@tprel at l([[REG1]])
-; CHECK: add {{[0-9]+}}, [[REG2]], a at tls
-
Removed: llvm/trunk/test/CodeGen/PowerPC/tls-ld-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls-ld-2.ll?rev=197080&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls-ld-2.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls-ld-2.ll (removed)
@@ -1,24 +0,0 @@
-; RUN: llc -mcpu=pwr7 -O1 -relocation-model=pic < %s | FileCheck %s
-
-; Test peephole optimization for thread-local storage using the
-; local dynamic model.
-
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
- at a = hidden thread_local global i32 0, align 4
-
-define signext i32 @main() nounwind {
-entry:
- %retval = alloca i32, align 4
- store i32 0, i32* %retval
- %0 = load i32* @a, align 4
- ret i32 %0
-}
-
-; CHECK: addis [[REG:[0-9]+]], 2, a at got@tlsld at ha
-; CHECK-NEXT: addi 3, [[REG]], a at got@tlsld at l
-; CHECK: bl __tls_get_addr(a at tlsld)
-; CHECK-NEXT: nop
-; CHECK: addis [[REG2:[0-9]+]], 3, a at dtprel@ha
-; CHECK-NEXT: lwa {{[0-9]+}}, a at dtprel@l([[REG2]])
Removed: llvm/trunk/test/CodeGen/PowerPC/tls-ld.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls-ld.ll?rev=197080&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls-ld.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls-ld.ll (removed)
@@ -1,24 +0,0 @@
-; RUN: llc -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck %s
-
-; Test correct assembly code generation for thread-local storage using
-; the local dynamic model.
-
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
- at a = hidden thread_local global i32 0, align 4
-
-define signext i32 @main() nounwind {
-entry:
- %retval = alloca i32, align 4
- store i32 0, i32* %retval
- %0 = load i32* @a, align 4
- ret i32 %0
-}
-
-; CHECK: addis [[REG:[0-9]+]], 2, a at got@tlsld at ha
-; CHECK-NEXT: addi 3, [[REG]], a at got@tlsld at l
-; CHECK: bl __tls_get_addr(a at tlsld)
-; CHECK-NEXT: nop
-; CHECK: addis [[REG2:[0-9]+]], 3, a at dtprel@ha
-; CHECK-NEXT: addi {{[0-9]+}}, [[REG2]], a at dtprel@l
Copied: llvm/trunk/test/CodeGen/PowerPC/tls-pic.ll (from r197072, llvm/trunk/test/CodeGen/PowerPC/tls-ld.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls-pic.ll?p2=llvm/trunk/test/CodeGen/PowerPC/tls-pic.ll&p1=llvm/trunk/test/CodeGen/PowerPC/tls-ld.ll&r1=197072&r2=197081&rev=197081&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls-ld.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls-pic.ll Wed Dec 11 16:25:39 2013
@@ -1,11 +1,9 @@
-; RUN: llc -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -march=ppc64 -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0 %s
+; RUN: llc -march=ppc64 -mcpu=pwr7 -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1 %s
; Test correct assembly code generation for thread-local storage using
; the local dynamic model.
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
@a = hidden thread_local global i32 0, align 4
define signext i32 @main() nounwind {
@@ -16,9 +14,41 @@ entry:
ret i32 %0
}
-; CHECK: addis [[REG:[0-9]+]], 2, a at got@tlsld at ha
-; CHECK-NEXT: addi 3, [[REG]], a at got@tlsld at l
-; CHECK: bl __tls_get_addr(a at tlsld)
-; CHECK-NEXT: nop
-; CHECK: addis [[REG2:[0-9]+]], 3, a at dtprel@ha
-; CHECK-NEXT: addi {{[0-9]+}}, [[REG2]], a at dtprel@l
+; OPT0-LABEL: main:
+; OPT0: addis [[REG:[0-9]+]], 2, a at got@tlsld at ha
+; OPT0-NEXT: addi 3, [[REG]], a at got@tlsld at l
+; OPT0: bl __tls_get_addr(a at tlsld)
+; OPT0-NEXT: nop
+; OPT0: addis [[REG2:[0-9]+]], 3, a at dtprel@ha
+; OPT0-NEXT: addi {{[0-9]+}}, [[REG2]], a at dtprel@l
+
+; Test peephole optimization for thread-local storage using the
+; local dynamic model.
+
+; OPT1-LABEL: main:
+; OPT1: addis [[REG:[0-9]+]], 2, a at got@tlsld at ha
+; OPT1-NEXT: addi 3, [[REG]], a at got@tlsld at l
+; OPT1: bl __tls_get_addr(a at tlsld)
+; OPT1-NEXT: nop
+; OPT1: addis [[REG2:[0-9]+]], 3, a at dtprel@ha
+; OPT1-NEXT: lwa {{[0-9]+}}, a at dtprel@l([[REG2]])
+
+; Test correct assembly code generation for thread-local storage using
+; the general dynamic model.
+
+ at a2 = thread_local global i32 0, align 4
+
+define signext i32 @main2() nounwind {
+entry:
+ %retval = alloca i32, align 4
+ store i32 0, i32* %retval
+ %0 = load i32* @a2, align 4
+ ret i32 %0
+}
+
+; OPT1-LABEL: main2
+; OPT1: addis [[REG:[0-9]+]], 2, a2 at got@tlsgd at ha
+; OPT1-NEXT: addi 3, [[REG]], a2 at got@tlsgd at l
+; OPT1: bl __tls_get_addr(a2 at tlsgd)
+; OPT1-NEXT: nop
+
Modified: llvm/trunk/test/CodeGen/PowerPC/tls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls.ll?rev=197081&r1=197080&r2=197081&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls.ll Wed Dec 11 16:25:39 2013
@@ -1,5 +1,3 @@
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-freebsd10.0"
; RUN: llc -O0 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT0 %s
; RUN: llc -O1 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT1 %s
@@ -19,3 +17,22 @@ entry:
store i32 42, i32* @a, align 4
ret i32 0
}
+
+; Test correct assembly code generation for thread-local storage
+; using the initial-exec model.
+
+ at a2 = external thread_local global i32
+
+define signext i32 @main2() nounwind {
+entry:
+ %retval = alloca i32, align 4
+ store i32 0, i32* %retval
+ %0 = load i32* @a2, align 4
+ ret i32 %0
+}
+
+; OPT1-LABEL: main2:
+; OPT1: addis [[REG1:[0-9]+]], 2, a2 at got@tprel at ha
+; OPT1: ld [[REG2:[0-9]+]], a2 at got@tprel at l([[REG1]])
+; OPT1: add {{[0-9]+}}, [[REG2]], a2 at tls
+
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