[PATCH] Add some missing intrinsics like vmull_high_n_s16 and friends

Jiangning Liu liujiangning1 at gmail.com
Mon Dec 2 04:15:45 PST 2013


  The newly added patterns all contain keyword "lane0".


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:4008
@@ -4008,2 +4007,3 @@
   if (hasDominantValue && EltSize <= 64) {
+    // Use VDUP for non-constant splats.
     if (!isConstant) {
----------------
This patch is using VDUP ISD, and the original comment is at incorrect location, so this patch covers this minor change.

================
Comment at: lib/Target/AArch64/AArch64InstrNEON.td:7344
@@ -7254,5 +7343,3 @@
 
-def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
-  let Inst{20-16} = 0b00100;
-  // bits 19-20 are unspecified, but should be set to zero.
-}
+  def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
+                       !cast<PatFrag>(op # "_4s"), 
----------------
newly added pattern for lane0.

================
Comment at: lib/Target/AArch64/AArch64InstrNEON.td:7348
@@ +7347,3 @@
+  
+  def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
+                       !cast<PatFrag>(op # "_2d"), 
----------------
newly added pattern for lane0.


http://llvm-reviews.chandlerc.com/D2301



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