[llvm] r195968 - Part 1 of 3 patches that completes very long conditional branches
Reed Kotler
rkotler at mips.com
Fri Nov 29 14:32:57 PST 2013
Author: rkotler
Date: Fri Nov 29 16:32:56 2013
New Revision: 195968
URL: http://llvm.org/viewvc/llvm-project?rev=195968&view=rev
Log:
Part 1 of 3 patches that completes very long conditional branches
in constant islands for Mips16. We introdcuce JalB16 as a synomnym
for Jal16. It makes it easier to read and is also necessary because
Jal16 is a call instruction but JalB16 is being used as a branch.
Various parts of LLVM will not work properly even in this late stage of
the backend if we use what was declared as a call instruction to function
as a branch. For one, basic block labels may not get emitted in some
situations.
Added:
llvm/trunk/test/CodeGen/Mips/lcb3c.ll
Modified:
llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp
Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td?rev=195968&r1=195967&r2=195968&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td Fri Nov 29 16:32:56 2013
@@ -120,6 +120,15 @@ class FJAL16_ins<bits<1> _X, string asms
itin> {
let isCodeGenOnly=1;
}
+
+class FJALB16_ins<bits<1> _X, string asmstr,
+ InstrItinClass itin>:
+ FJAL16<_X, (outs), (ins simm20:$imm),
+ !strconcat(asmstr, "\t$imm\t# branch\n\tnop"),[],
+ itin> {
+ let isCodeGenOnly=1;
+}
+
//
// EXT-I instruction format
//
@@ -737,6 +746,12 @@ def Jal16 : FJAL16_ins<0b0, "jal", IIAlu
let Defs = [RA];
}
+def JalB16 : FJALB16_ins<0b0, "jal", IIAlu>, branch16 {
+ let hasDelaySlot = 0; // not true, but we add the nop for now
+ let isBranch=1;
+ let Defs = [RA];
+}
+
//
// Format: JR ra MIPS16e
// Purpose: Jump Register Through Register ra
Modified: llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp?rev=195968&r1=195967&r2=195968&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp Fri Nov 29 16:32:56 2013
@@ -85,7 +85,7 @@ static unsigned int branchTargetOperand(
case Mips::BteqzX16:
case Mips::Btnez16:
case Mips::BtnezX16:
- case Mips::Jal16:
+ case Mips::JalB16:
return 0;
case Mips::BeqzRxImm16:
case Mips::BeqzRxImmX16:
@@ -96,6 +96,16 @@ static unsigned int branchTargetOperand(
llvm_unreachable("Unknown branch type");
}
+static bool isUnconditionalBranch(unsigned int Opcode) {
+ switch (Opcode) {
+ default: return false;
+ case Mips::Bimm16:
+ case Mips::BimmX16:
+ case Mips::JalB16:
+ return true;
+ }
+}
+
static unsigned int longformBranchOpcode(unsigned int Opcode) {
switch (Opcode) {
case Mips::Bimm16:
@@ -107,8 +117,8 @@ static unsigned int longformBranchOpcode
case Mips::Btnez16:
case Mips::BtnezX16:
return Mips::BtnezX16;
- case Mips::Jal16:
- return Mips::Jal16;
+ case Mips::JalB16:
+ return Mips::JalB16;
case Mips::BeqzRxImm16:
case Mips::BeqzRxImmX16:
return Mips::BeqzRxImmX16;
@@ -1561,7 +1571,7 @@ MipsConstantIslands::fixupUnconditionalB
//
DestBB->setAlignment(2);
Br.MaxDisp = ((1<<24)-1) * 2;
- MI->setDesc(TII->get(Mips::Jal16));
+ MI->setDesc(TII->get(Mips::JalB16));
}
BBInfo[MBB->getNumber()].Size += 2;
adjustBBOffsetsAfter(MBB);
@@ -1592,17 +1602,14 @@ MipsConstantIslands::fixupConditionalBr(
MI->setDesc(TII->get(LongFormOpcode));
return true;
}
- llvm_unreachable("Fixup of very long conditional branch not working yet.");
// Add an unconditional branch to the destination and invert the branch
// condition to jump over it:
- // blt L1
+ // bteqz L1
// =>
- // bge L2
+ // bnez L2
// b L1
// L2:
- unsigned CCReg = 0; // FIXME
- unsigned CC=0; //FIXME
// If the branch is at the end of its MBB and that has a fall-through block,
// direct the updated conditional branch to the fall-through block. Otherwise,
@@ -1611,28 +1618,34 @@ MipsConstantIslands::fixupConditionalBr(
MachineInstr *BMI = &MBB->back();
bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
+
++NumCBrFixed;
if (BMI != MI) {
if (llvm::next(MachineBasicBlock::iterator(MI)) == prior(MBB->end()) &&
- BMI->getOpcode() == Br.UncondBr) {
+ isUnconditionalBranch(BMI->getOpcode())) {
// Last MI in the BB is an unconditional branch. Can we simply invert the
// condition and swap destinations:
- // beq L1
+ // beqz L1
// b L2
// =>
- // bne L2
+ // bnez L2
// b L1
- MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
+ unsigned BMITargetOperand = branchTargetOperand(BMI);
+ MachineBasicBlock *NewDest =
+ BMI->getOperand(BMITargetOperand).getMBB();
if (isBBInRange(MI, NewDest, Br.MaxDisp)) {
DEBUG(dbgs() << " Invert Bcc condition and swap its destination with "
<< *BMI);
- BMI->getOperand(0).setMBB(DestBB);
- MI->getOperand(0).setMBB(NewDest);
+ MI->setDesc(TII->get(TII->getOppositeBranchOpc(Opcode)));
+ BMI->getOperand(BMITargetOperand).setMBB(DestBB);
+ MI->getOperand(TargetOperand).setMBB(NewDest);
return true;
}
}
}
+ llvm_unreachable("unsupported range of unconditional branch");
+
if (NeedSplit) {
splitBlockBeforeInstr(MI);
// No need for the branch to the next block. We're adding an unconditional
@@ -1651,7 +1664,7 @@ MipsConstantIslands::fixupConditionalBr(
// Insert a new conditional branch and a new unconditional branch.
// Also update the ImmBranch as well as adding a new entry for the new branch.
BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
- .addMBB(NextBB).addImm(CC).addReg(CCReg);
+ .addMBB(NextBB);
Br.MI = &MBB->back();
BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
Added: llvm/trunk/test/CodeGen/Mips/lcb3c.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/lcb3c.ll?rev=195968&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/lcb3c.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/lcb3c.ll Fri Nov 29 16:32:56 2013
@@ -0,0 +1,59 @@
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static -O0 < %s | FileCheck %s -check-prefix=lcb
+
+ at i = global i32 0, align 4
+ at j = common global i32 0, align 4
+ at k = common global i32 0, align 4
+
+; Function Attrs: nounwind
+define i32 @s() #0 {
+entry:
+ %0 = load i32* @i, align 4
+ %cmp = icmp eq i32 %0, 0
+ br i1 %cmp, label %if.then, label %if.else
+
+if.then: ; preds = %entry
+ store i32 0, i32* @i, align 4
+ call void asm sideeffect ".space 1000", ""() #1, !srcloc !1
+ br label %if.end
+
+if.else: ; preds = %entry
+ store i32 1, i32* @i, align 4
+ br label %if.end
+
+if.end: ; preds = %if.else, %if.then
+ ret i32 0
+; lcb: bnez $2, $BB0_2
+; lcb: b $BB0_1 # 16 bit inst
+; lcb: $BB0_1: # %if.then
+}
+
+; Function Attrs: nounwind
+define i32 @b() #0 {
+entry:
+ %0 = load i32* @i, align 4
+ %cmp = icmp eq i32 %0, 0
+ br i1 %cmp, label %if.then, label %if.else
+
+if.then: ; preds = %entry
+ store i32 0, i32* @i, align 4
+ call void asm sideeffect ".space 1000000", ""() #1, !srcloc !2
+ br label %if.end
+
+if.else: ; preds = %entry
+ store i32 1, i32* @i, align 4
+ br label %if.end
+
+if.end: ; preds = %if.else, %if.then
+ ret i32 0
+}
+
+; lcb: beqz $2, $BB1_1 # 16 bit inst
+; lcb: jal $BB1_2 # branch
+; lcb: $BB1_1: # %if.then
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind }
+
+
+!1 = metadata !{i32 65}
+!2 = metadata !{i32 167}
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