[llvm] r195881 - R600: Expand vector FABS

[Tom Stellard]

Hi Bill,

Can you merge this patch into the 3.4 branch?  I am the code owner, and
I approve this commit.

Thanks,
Tom

On Wed, Nov 27, 2013 at 09:23:40PM -0000, Tom Stellard wrote:
> Author: tstellar
> Date: Wed Nov 27 15:23:39 2013
> New Revision: 195881
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=195881&view=rev
> Log:
> R600: Expand vector FABS
> 
> NOTE: This is a candidate for the 3.4 branch.
> 
> Modified:
>     llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
>     llvm/trunk/test/CodeGen/R600/fabs.ll
> 
> Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=195881&r1=195880&r2=195881&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp Wed Nov 27 15:23:39 2013
> @@ -179,6 +179,7 @@ AMDGPUTargetLowering::AMDGPUTargetLoweri
>  
>    for (unsigned int x = 0; x < NumFloatTypes; ++x) {
>      MVT::SimpleValueType VT = FloatTypes[x];
> +    setOperationAction(ISD::FABS, VT, Expand);
>      setOperationAction(ISD::FADD, VT, Expand);
>      setOperationAction(ISD::FDIV, VT, Expand);
>      setOperationAction(ISD::FFLOOR, VT, Expand);
> 
> Modified: llvm/trunk/test/CodeGen/R600/fabs.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fabs.ll?rev=195881&r1=195880&r2=195881&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/fabs.ll (original)
> +++ llvm/trunk/test/CodeGen/R600/fabs.ll Wed Nov 27 15:23:39 2013
> @@ -5,10 +5,10 @@
>  ; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
>  ; unless isFabsFree returns true
>  
> -; R600-CHECK: @fabs_free
> +; R600-CHECK-LABEL: @fabs_free
>  ; R600-CHECK-NOT: AND
>  ; R600-CHECK: |PV.{{[XYZW]}}|
> -; SI-CHECK: @fabs_free
> +; SI-CHECK-LABEL: @fabs_free
>  ; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
>  
>  define void @fabs_free(float addrspace(1)* %out, i32 %in) {
> @@ -19,4 +19,36 @@ entry:
>    ret void
>  }
>  
> +; R600-CHECK-LABEL: @fabs_v2
> +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
> +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
> +; SI-CHECK-LABEL: @fabs_v2
> +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
> +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
> +define void @fabs_v2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
> +entry:
> +  %0 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
> +  store <2 x float> %0, <2 x float> addrspace(1)* %out
> +  ret void
> +}
> +
> +; R600-CHECK-LABEL: @fabs_v4
> +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
> +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
> +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
> +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
> +; SI-CHECK-LABEL: @fabs_v4
> +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
> +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
> +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
> +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
> +define void @fabs_v4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
> +entry:
> +  %0 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
> +  store <4 x float> %0, <4 x float> addrspace(1)* %out
> +  ret void
> +}
> +
>  declare float @fabs(float ) readnone
> +declare <2 x float> @llvm.fabs.v2f32(<2 x float> ) readnone
> +declare <4 x float> @llvm.fabs.v4f32(<4 x float> ) readnone
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits