[llvm] r195444 - [mips][msa] Float vector constants cannot use ldi.[wd] directly. Bitcast from the appropriate integer vector type.

[Daniel Sanders]

Hi Chris,

There doesn't seem to be an owner for the MIPS backend in CODE_OWNERS.txt. Can you approve merging this commit to the release_34 branch?

Just to give you the context, it's part of the following series of patches:
* r195343 - [mips][msa/dsp] Only do DSP combines if DSP is enabled.
* r195364 - [mips][msa] Fix a corner case in performORCombine() when combining nodes into VSELECT. 
* r195444 - [mips][msa] Float vector constants cannot use ldi.[wd] directly. Bitcast from the appropriate integer vector type.
* r195455, r195456, and r195469 - [mips][msa] Fix corner case for integer constant splats with undef values. 
Once these four patches are committed, an llvm-stress + llc loop can run for over 15 hours without llc crashing (up from a previous best of ~20 seconds).

> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
> bounces at cs.uiuc.edu] On Behalf Of Daniel Sanders
> Sent: 22 November 2013 11:25
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm] r195444 - [mips][msa] Float vector constants cannot use
> ldi.[wd] directly. Bitcast from the appropriate integer vector type.
> 
> Author: dsanders
> Date: Fri Nov 22 05:24:50 2013
> New Revision: 195444
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=195444&view=rev
> Log:
> [mips][msa] Float vector constants cannot use ldi.[wd] directly. Bitcast from
> the appropriate integer vector type.
> 
> Fixes an instruction selection failure detected by llvm-stress.
> 
> Added:
>     llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll
> Modified:
>     llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
> 
> Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=195444&r1
> =195443&r2=195444&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp Fri Nov 22
> +++ 05:24:50 2013
> @@ -2210,7 +2210,9 @@ SDValue MipsSETargetLowering::lowerBUILD
>        return SDValue();
> 
>      // If the value fits into a simm10 then we can use ldi.[bhwd]
> -    if (SplatValue.isSignedIntN(10))
> +    // However, if it isn't an integer type we will have to bitcast from an
> +    // integer type first.
> +    if (ResTy.isInteger() && SplatValue.isSignedIntN(10))
>        return Op;
> 
>      EVT ViaVecTy;
> 
> Added: llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2501752154-
> simplified.ll
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2501752154-
> simplified.ll?rev=195444&view=auto
> ==========================================================
> ====================
> --- llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll
> (added)
> +++ llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s2501752154-
> simplified.
> +++ ll Fri Nov 22 05:24:50 2013
> @@ -0,0 +1,27 @@
> +; RUN: llc -march=mips < %s
> +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s ; RUN: llc -march=mipsel
> +< %s ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
> +
> +; This test originally failed for MSA with a "Cannot select ..." error.
> +; This happened because the legalizer treated undef's in the <4 x
> +float> ; constant as equivalent to the defined elements when checking
> +if it a constant ; splat, but then proceeded to legalize the undef's to
> +zero, leaving it as a ; non-splat that cannot be selected. It should
> +have eliminated the undef's by ; rewriting the splat constant.
> +
> +; It should at least successfully build.
> +
> +define void @autogen_SD2501752154() {
> +BB:
> +  %BC = bitcast <4 x i32> <i32 -1, i32 -1, i32 undef, i32 undef> to <4
> +x float>
> +  br label %CF74
> +
> +CF74:                                             ; preds = %CF74, %CF
> +  %E54 = extractelement <1 x i1> undef, i32 0
> +  br i1 %E54, label %CF74, label %CF79
> +
> +CF79:                                             ; preds = %CF75
> +  %I63 = insertelement <4 x float> %BC, float undef, i32 0
> +  ret void
> +}
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits