[PATCH] implement MC layer of AArch64 neon instruction pmull and pmull2 with 128 bit integer

[Kevin Qin]

Please review, thanks.

http://llvm-reviews.chandlerc.com/D2213

Files:
  lib/Target/AArch64/AArch64InstrNEON.td
  lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  test/MC/AArch64/neon-3vdiff.s
  test/MC/AArch64/neon-diagnostics.s

Index: lib/Target/AArch64/AArch64InstrNEON.td
===================================================================
--- lib/Target/AArch64/AArch64InstrNEON.td
+++ lib/Target/AArch64/AArch64InstrNEON.td
@@ -3284,6 +3284,11 @@
   let isCommutable = Commutable in {
     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
                               opnode, VPR128, VPR64, v8i16, v8i8>;
+    
+    def _1q1d : NeonI_3VDiff<0b0, u, 0b11, opcode,
+                             (outs VPR128:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
+                             asmop # "\t$Rd.1q, $Rn.1d, $Rm.1d",
+                             [], NoItinerary>;
   }
 }
 
@@ -3295,6 +3300,11 @@
     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
                                       !cast<PatFrag>(opnode # "_16B"),
                                       v8i16, v16i8>;
+    
+    def _1q2d : NeonI_3VDiff<0b1, u, 0b11, opcode,
+                             (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
+                             asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
+                             [], NoItinerary>;
   }
 }
 
Index: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1639,6 +1639,7 @@
 
     // See if it's a 128-bit layout first.
     Layout = StringSwitch<const char *>(LayoutText)
+      .Case(".q", ".q").Case(".1q", ".1q")
       .Case(".d", ".d").Case(".2d", ".2d")
       .Case(".s", ".s").Case(".4s", ".4s")
       .Case(".h", ".h").Case(".8h", ".8h")
@@ -1737,6 +1738,7 @@
       case 'h': NumLanes = 8; break;
       case 's': NumLanes = 4; break;
       case 'd': NumLanes = 2; break;
+      case 'q': NumLanes = 1; break;
       }
     }
 
Index: test/MC/AArch64/neon-3vdiff.s
===================================================================
--- test/MC/AArch64/neon-3vdiff.s
+++ test/MC/AArch64/neon-3vdiff.s
@@ -283,12 +283,16 @@
 //------------------------------------------------------------------------------
 
         pmull v0.8h, v1.8b, v2.8b
+        pmull v0.1q, v1.1d, v2.1d
 
 // CHECK: pmull	v0.8h, v1.8b, v2.8b     // encoding: [0x20,0xe0,0x22,0x0e]
+// CHECK: pmull	v0.1q, v1.1d, v2.1d     // encoding: [0x20,0xe0,0xe2,0x0e]
 
         pmull2 v0.8h, v1.16b, v2.16b
+        pmull2 v0.1q, v1.2d, v2.2d
 
 // CHECK: pmull2	v0.8h, v1.16b, v2.16b   // encoding: [0x20,0xe0,0x22,0x4e]
+// CHECK: pmull2	v0.1q, v1.2d, v2.2d     // encoding: [0x20,0xe0,0xe2,0x4e]
 
 //------------------------------------------------------------------------------
 // Widen
Index: test/MC/AArch64/neon-diagnostics.s
===================================================================
--- test/MC/AArch64/neon-diagnostics.s
+++ test/MC/AArch64/neon-diagnostics.s
@@ -2582,6 +2582,12 @@
 // CHECK-ERROR:        pmull v0.8h, v1.8h, v2.8b
 // CHECK-ERROR:                        ^
 
+        pmull v0.1q, v1.2d, v2.2d
+        
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        pmull v0.1q, v1.2d, v2.2d
+// CHECK-ERROR:                     ^
+
         // Mismatched vector types
         pmull v0.4s, v1.4h, v2.4h
         pmull v0.2d, v1.2s, v2.2s
@@ -2600,6 +2606,12 @@
 // CHECK-ERROR:        pmull2 v0.8h, v1.16h, v2.16b
 // CHECK-ERROR:                      ^
 
+        pmull2 v0.q, v1.2d, v2.2d
+        
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        pmull2 v0.q, v1.2d, v2.2d
+// CHECK-ERROR:                  ^
+
         // Mismatched vector types
         pmull2 v0.4s, v1.8h v2.8h
         pmull2 v0.2d, v1.4s, v2.4s
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