[llvm] r194592 - Enable generating legacy IT block for AArch32
Weiming Zhao
weimingz at codeaurora.org
Wed Nov 13 10:29:50 PST 2013
Author: weimingz
Date: Wed Nov 13 12:29:49 2013
New Revision: 194592
URL: http://llvm.org/viewvc/llvm-project?rev=194592&view=rev
Log:
Enable generating legacy IT block for AArch32
By default, the behavior of IT block generation will be determinated
dynamically base on the arch (armv8 vs armv7). This patch adds backend
options: -arm-restrict-it and -arm-no-restrict-it. The former one
restricts the generation of IT blocks (the same behavior as thumbv8) for
both arches. The later one allows the generation of legacy IT block (the
same behavior as ARMv7 Thumb2) for both arches.
Clang will support -mrestrict-it and -mno-restrict-it, which is
compatible with GCC.
Modified:
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
llvm/trunk/lib/Target/ARM/ARMSubtarget.h
llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
llvm/trunk/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt3.ll
llvm/trunk/test/CodeGen/Thumb2/v8_IT_1.ll
llvm/trunk/test/CodeGen/Thumb2/v8_IT_2.ll
llvm/trunk/test/CodeGen/Thumb2/v8_IT_3.ll
llvm/trunk/test/CodeGen/Thumb2/v8_IT_4.ll
llvm/trunk/test/CodeGen/Thumb2/v8_IT_5.ll
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=194592&r1=194591&r2=194592&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Nov 13 12:29:49 2013
@@ -525,7 +525,7 @@ bool ARMBaseInstrInfo::isPredicable(Mach
MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
if (AFI->isThumb2Function()) {
- if (getSubtarget().hasV8Ops())
+ if (getSubtarget().restrictIT())
return isV8EligibleForIT(MI);
} else { // non-Thumb
if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=194592&r1=194591&r2=194592&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Wed Nov 13 12:29:49 2013
@@ -57,6 +57,23 @@ Align(cl::desc("Load/store alignment sup
"Allow unaligned memory accesses"),
clEnumValEnd));
+enum ITMode {
+ DefaultIT,
+ RestrictedIT,
+ NoRestrictedIT
+};
+
+static cl::opt<ITMode>
+IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
+ cl::ZeroOrMore,
+ cl::values(clEnumValN(DefaultIT, "arm-default-it",
+ "Generate IT block based on arch"),
+ clEnumValN(RestrictedIT, "arm-restrict-it",
+ "Disallow deprecated IT based on ARMv8"),
+ clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
+ "Allow IT blocks based on ARMv7"),
+ clEnumValEnd));
+
ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, const TargetOptions &Options)
: ARMGenSubtargetInfo(TT, CPU, FS)
@@ -217,6 +234,18 @@ void ARMSubtarget::resetSubtargetFeature
break;
}
+ switch (IT) {
+ case DefaultIT:
+ RestrictIT = hasV8Ops() ? true : false;
+ break;
+ case RestrictedIT:
+ RestrictIT = true;
+ break;
+ case NoRestrictedIT:
+ RestrictIT = false;
+ break;
+ }
+
// NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
uint64_t Bits = getFeatureBits();
if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=194592&r1=194591&r2=194592&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Wed Nov 13 12:29:49 2013
@@ -177,6 +177,10 @@ protected:
/// ARMTargetLowering::allowsUnalignedMemoryAccesses().
bool AllowsUnalignedMem;
+ /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
+ /// blocks to conform to ARMv8 rule.
+ bool RestrictIT;
+
/// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
/// and such) instructions in Thumb2 code.
bool Thumb2DSP;
@@ -327,6 +331,8 @@ public:
bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
+ bool restrictIT() const { return RestrictIT; }
+
const std::string & getCPUString() const { return CPUString; }
unsigned getMispredictionPenalty() const;
Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=194592&r1=194591&r2=194592&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Nov 13 12:29:49 2013
@@ -198,7 +198,7 @@ bool ARMPassConfig::addPreSched2() {
if (getOptLevel() != CodeGenOpt::None) {
if (!getARMSubtarget().isThumb1Only()) {
// in v8, IfConversion depends on Thumb instruction widths
- if (getARMSubtarget().hasV8Ops() &&
+ if (getARMSubtarget().restrictIT() &&
!getARMSubtarget().prefers32BitThumb())
addPass(createThumb2SizeReductionPass());
addPass(&IfConverterID);
Modified: llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=194592&r1=194591&r2=194592&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Wed Nov 13 12:29:49 2013
@@ -28,7 +28,7 @@ namespace {
static char ID;
Thumb2ITBlockPass() : MachineFunctionPass(ID) {}
- bool hasV8Ops;
+ bool restrictIT;
const Thumb2InstrInfo *TII;
const TargetRegisterInfo *TRI;
ARMFunctionInfo *AFI;
@@ -194,8 +194,9 @@ bool Thumb2ITBlockPass::InsertITInstruct
ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
unsigned Mask = 0, Pos = 3;
- // v8 IT blocks are limited to one conditional op: skip the loop
- if (!hasV8Ops) {
+ // v8 IT blocks are limited to one conditional op unless -arm-no-restrict-it
+ // is set: skip the loop
+ if (!restrictIT) {
// Branches, including tricky ones like LDM_RET, need to end an IT
// block so check the instruction we just put in the block.
for (; MBBI != E && Pos &&
@@ -255,7 +256,7 @@ bool Thumb2ITBlockPass::runOnMachineFunc
AFI = Fn.getInfo<ARMFunctionInfo>();
TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
TRI = TM.getRegisterInfo();
- hasV8Ops = TM.getSubtarget<ARMSubtarget>().hasV8Ops();
+ restrictIT = TM.getSubtarget<ARMSubtarget>().restrictIT();
if (!AFI->isThumbFunction())
return false;
Modified: llvm/trunk/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll?rev=194592&r1=194591&r2=194592&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll Wed Nov 13 12:29:49 2013
@@ -1,5 +1,6 @@
; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s
; RUN: llc < %s -mtriple=thumbv8 | FileCheck -check-prefix=CHECK-V8 %s
+; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it | FileCheck -check-prefix=CHECK-V8 %s
; rdar://13782395
define i32 @t1(i32 %a, i32 %b, i8** %retaddr) {
Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll?rev=194592&r1=194591&r2=194592&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll Wed Nov 13 12:29:49 2013
@@ -1,5 +1,6 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
-
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-default-it | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv8 -arm-no-restrict-it |FileCheck %s
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; CHECK-LABEL: t1:
; CHECK: ittt ne
@@ -74,7 +75,7 @@ entry:
; CHECK-LABEL: t3:
; CHECK: itt ge
; CHECK: movge r0, r1
-; CHECK: blge _foo
+; CHECK: blge {{_?}}foo
%tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1]
br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll?rev=194592&r1=194591&r2=194592&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll Wed Nov 13 12:29:49 2013
@@ -1,4 +1,6 @@
; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-ios -arm-default-it | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv8-apple-ios -arm-no-restrict-it | FileCheck %s
define void @foo(i32 %X, i32 %Y) {
entry:
Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt3.ll?rev=194592&r1=194591&r2=194592&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt3.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt3.ll Wed Nov 13 12:29:49 2013
@@ -1,4 +1,6 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-default-it | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv8-apple-darwin -arm-no-restrict-it | FileCheck %s
; There shouldn't be a unconditional branch at end of bb52.
; rdar://7184787
Modified: llvm/trunk/test/CodeGen/Thumb2/v8_IT_1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/v8_IT_1.ll?rev=194592&r1=194591&r2=194592&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/v8_IT_1.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/v8_IT_1.ll Wed Nov 13 12:29:49 2013
@@ -1,4 +1,5 @@
; RUN: llc < %s -mtriple=thumbv8 -mattr=+neon | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7 -mattr=+neon -arm-restrict-it | FileCheck %s
;CHECK-LABEL: select_s_v_v:
;CHECK-NOT: it
Modified: llvm/trunk/test/CodeGen/Thumb2/v8_IT_2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/v8_IT_2.ll?rev=194592&r1=194591&r2=194592&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/v8_IT_2.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/v8_IT_2.ll Wed Nov 13 12:29:49 2013
@@ -1,4 +1,5 @@
; RUN: llc < %s -mtriple=thumbv8 | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it | FileCheck %s
%struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }
Modified: llvm/trunk/test/CodeGen/Thumb2/v8_IT_3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/v8_IT_3.ll?rev=194592&r1=194591&r2=194592&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/v8_IT_3.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/v8_IT_3.ll Wed Nov 13 12:29:49 2013
@@ -1,5 +1,7 @@
; RUN: llc < %s -mtriple=thumbv8 | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it | FileCheck %s
; RUN: llc < %s -mtriple=thumbv8 -relocation-model=pic | FileCheck %s --check-prefix=CHECK-PIC
+; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it -relocation-model=pic | FileCheck %s --check-prefix=CHECK-PIC
%struct.FF = type { i32 (i32*)*, i32 (i32*, i32*, i32, i32, i32, i32)*, i32 (i32, i32, i8*)*, void ()*, i32 (i32, i8*, i32*)*, i32 ()* }
%struct.BD = type { %struct.BD*, i32, i32, i32, i32, i64, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i64, i32)*, [16 x i8], i64, i64 }
Modified: llvm/trunk/test/CodeGen/Thumb2/v8_IT_4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/v8_IT_4.ll?rev=194592&r1=194591&r2=194592&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/v8_IT_4.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/v8_IT_4.ll Wed Nov 13 12:29:49 2013
@@ -1,5 +1,7 @@
; RUN: llc < %s -mtriple=thumbv8-eabi -float-abi=hard | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-eabi -float-abi=hard -arm-restrict-it | FileCheck %s
; RUN: llc < %s -mtriple=thumbv8-eabi -float-abi=hard -regalloc=basic | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-eabi -float-abi=hard -regalloc=basic -arm-restrict-it | FileCheck %s
%"struct.__gnu_cxx::__normal_iterator<char*,std::basic_string<char, std::char_traits<char>, std::allocator<char> > >" = type { i8* }
%"struct.__gnu_cxx::new_allocator<char>" = type <{ i8 }>
Modified: llvm/trunk/test/CodeGen/Thumb2/v8_IT_5.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/v8_IT_5.ll?rev=194592&r1=194591&r2=194592&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/v8_IT_5.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/v8_IT_5.ll Wed Nov 13 12:29:49 2013
@@ -1,4 +1,5 @@
; RUN: llc < %s -mtriple=thumbv8 | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it | FileCheck %s
; CHECK: it ne
; CHECK-NEXT: cmpne
; CHECK-NEXT: beq
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