[llvm] r194585 - [SystemZ] Add the general form of BCR
Richard Sandiford
rsandifo at linux.vnet.ibm.com
Wed Nov 13 08:57:53 PST 2013
Author: rsandifo
Date: Wed Nov 13 10:57:53 2013
New Revision: 194585
URL: http://llvm.org/viewvc/llvm-project?rev=194585&view=rev
Log:
[SystemZ] Add the general form of BCR
At the moment this is just the MC support.
Modified:
llvm/trunk/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
llvm/trunk/test/MC/SystemZ/insn-bad.s
llvm/trunk/test/MC/SystemZ/insn-good.s
Modified: llvm/trunk/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp?rev=194585&r1=194584&r2=194585&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp Wed Nov 13 10:57:53 2013
@@ -48,14 +48,11 @@ extern "C" void LLVMInitializeSystemZDis
}
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
- const unsigned *Regs,
- bool isAddress = false) {
+ const unsigned *Regs) {
assert(RegNo < 16 && "Invalid register");
- if (!isAddress || RegNo) {
- RegNo = Regs[RegNo];
- if (RegNo == 0)
- return MCDisassembler::Fail;
- }
+ RegNo = Regs[RegNo];
+ if (RegNo == 0)
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateReg(RegNo));
return MCDisassembler::Success;
}
@@ -87,7 +84,7 @@ static DecodeStatus DecodeGR128BitRegist
static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, true);
+ return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs);
}
static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=194585&r1=194584&r2=194585&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Wed Nov 13 10:57:53 2013
@@ -67,6 +67,8 @@ let isBranch = 1, isTerminator = 1, Uses
"brc\t$R1, $I2", []>;
def AsmBRCL : InstRIL<0xC04, (outs), (ins uimm8zx4:$R1, brtarget32:$I2),
"brcl\t$R1, $I2", []>;
+ def AsmBCR : InstRR<0x07, (outs), (ins uimm8zx4:$R1, GR64:$R2),
+ "bcr\t$R1, $R2", []>;
}
// Fused compare-and-branch instructions. As for normal branches,
@@ -117,6 +119,7 @@ multiclass CondExtendedMnemonic<bits<4>
"j"##name##"\t$I2", []>;
def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
"jg"##name##"\t$I2", []>;
+ def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), "b"##name##"r\t$R2", []>;
}
def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>;
def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=194585&r1=194584&r2=194585&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Wed Nov 13 10:57:53 2013
@@ -790,6 +790,51 @@
# CHECK: basr %r15, %r1
0x0d 0xf1
+# CHECK: bcr 0, %r14
+0x07 0x0e
+
+# CHECK: bor %r13
+0x07 0x1d
+
+# CHECK: bhr %r12
+0x07 0x2c
+
+# CHECK: bnler %r11
+0x07 0x3b
+
+# CHECK: blr %r10
+0x07 0x4a
+
+# CHECK: bnher %r9
+0x07 0x59
+
+# CHECK: blhr %r8
+0x07 0x68
+
+# CHECK: bner %r7
+0x07 0x77
+
+# CHECK: ber %r6
+0x07 0x86
+
+# CHECK: bnlhr %r5
+0x07 0x95
+
+# CHECK: bher %r4
+0x07 0xa4
+
+# CHECK: bnlr %r3
+0x07 0xb3
+
+# CHECK: bler %r2
+0x07 0xc2
+
+# CHECK: bnhr %r1
+0x07 0xd1
+
+# CHECK: bnor %r0
+0x07 0xe0
+
# CHECK: br %r1
0x07 0xf1
Modified: llvm/trunk/test/MC/SystemZ/insn-bad.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad.s?rev=194585&r1=194584&r2=194585&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad.s Wed Nov 13 10:57:53 2013
@@ -256,6 +256,14 @@
ay %r0, -524289
ay %r0, 524288
+#CHECK: error: invalid operand
+#CHECK: bcr -1, %r1
+#CHECK: error: invalid operand
+#CHECK: bcr 16, %r1
+
+ bcr -1, %r1
+ bcr 16, %r1
+
#CHECK: error: offset out of range
#CHECK: bras %r0, -0x100002
#CHECK: error: offset out of range
Modified: llvm/trunk/test/MC/SystemZ/insn-good.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good.s?rev=194585&r1=194584&r2=194585&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good.s Wed Nov 13 10:57:53 2013
@@ -527,11 +527,102 @@
basr %r14,%r9
basr %r15,%r1
+#CHECK: bcr 0, %r0 # encoding: [0x07,0x00]
+#CHECK: bcr 0, %r15 # encoding: [0x07,0x0f]
+ bcr 0, %r0
+ bcr 0, %r15
+
+#CHECK: bcr 1, %r7 # encoding: [0x07,0x17]
+#CHECK: bor %r15 # encoding: [0x07,0x1f]
+
+ bcr 1, %r7
+ bor %r15
+
+#CHECK: bcr 2, %r7 # encoding: [0x07,0x27]
+#CHECK: bhr %r15 # encoding: [0x07,0x2f]
+
+ bcr 2, %r7
+ bhr %r15
+
+#CHECK: bcr 3, %r7 # encoding: [0x07,0x37]
+#CHECK: bnler %r15 # encoding: [0x07,0x3f]
+
+ bcr 3, %r7
+ bnler %r15
+
+#CHECK: bcr 4, %r7 # encoding: [0x07,0x47]
+#CHECK: blr %r15 # encoding: [0x07,0x4f]
+
+ bcr 4, %r7
+ blr %r15
+
+#CHECK: bcr 5, %r7 # encoding: [0x07,0x57]
+#CHECK: bnher %r15 # encoding: [0x07,0x5f]
+
+ bcr 5, %r7
+ bnher %r15
+
+#CHECK: bcr 6, %r7 # encoding: [0x07,0x67]
+#CHECK: blhr %r15 # encoding: [0x07,0x6f]
+
+ bcr 6, %r7
+ blhr %r15
+
+#CHECK: bcr 7, %r7 # encoding: [0x07,0x77]
+#CHECK: bner %r15 # encoding: [0x07,0x7f]
+
+ bcr 7, %r7
+ bner %r15
+
+#CHECK: bcr 8, %r7 # encoding: [0x07,0x87]
+#CHECK: ber %r15 # encoding: [0x07,0x8f]
+
+ bcr 8, %r7
+ ber %r15
+
+#CHECK: bcr 9, %r7 # encoding: [0x07,0x97]
+#CHECK: bnlhr %r15 # encoding: [0x07,0x9f]
+
+ bcr 9, %r7
+ bnlhr %r15
+
+#CHECK: bcr 10, %r7 # encoding: [0x07,0xa7]
+#CHECK: bher %r15 # encoding: [0x07,0xaf]
+
+ bcr 10, %r7
+ bher %r15
+
+#CHECK: bcr 11, %r7 # encoding: [0x07,0xb7]
+#CHECK: bnlr %r15 # encoding: [0x07,0xbf]
+
+ bcr 11, %r7
+ bnlr %r15
+
+#CHECK: bcr 12, %r7 # encoding: [0x07,0xc7]
+#CHECK: bler %r15 # encoding: [0x07,0xcf]
+
+ bcr 12, %r7
+ bler %r15
+
+#CHECK: bcr 13, %r7 # encoding: [0x07,0xd7]
+#CHECK: bnhr %r15 # encoding: [0x07,0xdf]
+
+ bcr 13, %r7
+ bnhr %r15
+
+#CHECK: bcr 14, %r7 # encoding: [0x07,0xe7]
+#CHECK: bnor %r15 # encoding: [0x07,0xef]
+
+ bcr 14, %r7
+ bnor %r15
+
+#CHECK: bcr 15, %r7 # encoding: [0x07,0xf7]
#CHECK: br %r1 # encoding: [0x07,0xf1]
#CHECK: br %r14 # encoding: [0x07,0xfe]
#CHECK: br %r15 # encoding: [0x07,0xff]
+ bcr 15, %r7
br %r1
br %r14
br %r15
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