[llvm] r194416 - [ARM] Add support for MVFR2 which is new in ARMv8

[Artyom Skrobov]

Author: askrobov
Date: Mon Nov 11 13:56:13 2013
New Revision: 194416

URL: http://llvm.org/viewvc/llvm-project?rev=194416&view=rev
Log:
[ARM] Add support for MVFR2 which is new in ARMv8

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
    llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
    llvm/trunk/test/MC/ARM/fp-armv8.s
    llvm/trunk/test/MC/Disassembler/ARM/fp-armv8.txt
    llvm/trunk/test/MC/Disassembler/ARM/invalid-because-armv7.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=194416&r1=194415&r2=194416&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Nov 11 13:56:13 2013
@@ -1546,6 +1546,8 @@ let Uses = [FPSCR] in {
                               "vmrs", "\t$Rt, mvfr0", []>;
   def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
                               "vmrs", "\t$Rt, mvfr1", []>;
+  def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins),
+                              "vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>;
   def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
                               "vmrs", "\t$Rt, fpinst", []>;
   def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=194416&r1=194415&r2=194416&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Mon Nov 11 13:56:13 2013
@@ -172,6 +172,7 @@ def ITSTATE    : ARMReg<4, "itstate">;
 
 // Special Registers - only available in privileged mode.
 def FPSID   : ARMReg<0,  "fpsid">;
+def MVFR2   : ARMReg<5,  "mvfr2">;
 def MVFR1   : ARMReg<6,  "mvfr1">;
 def MVFR0   : ARMReg<7,  "mvfr0">;
 def FPEXC   : ARMReg<8,  "fpexc">;

Modified: llvm/trunk/test/MC/ARM/fp-armv8.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/fp-armv8.s?rev=194416&r1=194415&r2=194416&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/fp-armv8.s (original)
+++ llvm/trunk/test/MC/ARM/fp-armv8.s Mon Nov 11 13:56:13 2013
@@ -122,3 +122,8 @@
 @ CHECK: vrintm.f64 d3, d4     @ encoding: [0x44,0x3b,0xbb,0xfe]
   vrintm.f32 s12, s1
 @ CHECK: vrintm.f32 s12, s1    @ encoding: [0x60,0x6a,0xbb,0xfe]
+
+@ MVFR2
+
+  vmrs sp, mvfr2
+@ CHECK: vmrs sp, mvfr2        @ encoding: [0x10,0xda,0xf5,0xee]

Modified: llvm/trunk/test/MC/Disassembler/ARM/fp-armv8.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/fp-armv8.txt?rev=194416&r1=194415&r2=194416&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/fp-armv8.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/fp-armv8.txt Mon Nov 11 13:56:13 2013
@@ -153,3 +153,8 @@
 
 0x60 0x6a 0xbb 0xfe
 # CHECK: vrintm.f32 s12, s1
+
+
+0x10 0xa 0xf5 0xee
+# CHECK: vmrs r0, mvfr2
+

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-because-armv7.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-because-armv7.txt?rev=194416&r1=194415&r2=194416&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-because-armv7.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-because-armv7.txt Mon Nov 11 13:56:13 2013
@@ -18,3 +18,9 @@
 [0x41 0x2b 0xb3 0xbe]
 # CHECK: invalid instruction encoding
 # CHECK-NEXT: [0x41 0x2b 0xb3 0xbe]
+
+# Would be vmrs r0, mvfr2
+[0x10 0xa 0xf5 0xee]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x10 0xa 0xf5 0xee]
+