[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8

[Artyom Skrobov]

Hello,

 

v8 ARMARM has restricted the list of coprocessors supported in AArch32 to
the four required for the legacy code.

(Section E1.4 Coprocessor support: The only supported coprocessors in ARMv8
are CP15, CP14, CP10 and CP11.)

 

The coprocessor instructions operating on any coprocessors not in this list
are to be undefined, starting from ARMv8.

(e.g. Section F7.1.204: If no coprocessor can execute the instruction, an
Undefined Instruction exception is generated.)

 

CP10 and CP11, used for the FP/NEON operations, are already excluded from
the list of valid operands for the generic coprocessor instructions.

We're proposing a patchset to further restrict the valid ranges for
coprocessor operands, starting from ARMv8, as specified in Section G3.15.2:

 

* STC and LDC are only defined for CP14

* MCRR, MRRC, MRC, MCR are defined for CP14 and CP15

* CDP, CDP2, MCR2, MRC2, MCRR2, MRRC2, LDC2, STC2 are no longer defined for
any coprocessor

 

Our patchset consists of three patches. The first one exports
getSubtargetInfo() from MCDisassembler public interface, to allow
architecture-aware disassembly, which had not been required until now. The
two other patches implement the necessary changes for ARM and Thumb
encodings, correspondingly. The last patch also deletes 4KLOC from
test/MC/ARM/v8_IT_manual.s - these tested a bunch of encodings which are in
fact invalid.

 

OK to commit this?
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