[PATCH] R600/SI: Display neg/abs operand the same way as R600
Tom Stellard
tom at stellard.net
Mon Oct 21 12:29:54 PDT 2013
On Mon, Oct 21, 2013 at 03:03:46PM +0200, Vincent Lejeune wrote:
> ---
> lib/Target/R600/AMDGPUInstructions.td | 9 +++++-
> lib/Target/R600/R600Instructions.td | 7 -----
> lib/Target/R600/SIISelLowering.cpp | 45 +++++++++++++++++++++++---
> lib/Target/R600/SIInstrFormats.td | 24 ++++++++++----
> lib/Target/R600/SIInstrInfo.td | 59 ++++++++++++++++++++++++-----------
> lib/Target/R600/SIInstructions.td | 24 ++++++--------
> test/CodeGen/R600/fabs.ll | 2 +-
> test/CodeGen/R600/fneg.ll | 23 ++++++++------
> test/CodeGen/R600/fsub64.ll | 2 +-
> test/CodeGen/R600/seto.ll | 2 +-
> test/CodeGen/R600/setuo.ll | 2 +-
> 11 files changed, 136 insertions(+), 63 deletions(-)
>
I'm not a huge fan of adding all these extra operands, but I'm not sure
there is a better way to get the assembly output we want.
This patch is:
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
> diff --git a/lib/Target/R600/AMDGPUInstructions.td b/lib/Target/R600/AMDGPUInstructions.td
> index 5778a8c..e5df14c 100644
> --- a/lib/Target/R600/AMDGPUInstructions.td
> +++ b/lib/Target/R600/AMDGPUInstructions.td
> @@ -34,7 +34,14 @@ class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
>
> }
>
> -def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
> +class InstFlag<string PM = "printOperand", int Default = 0>
> + : OperandWithDefaultOps <i32, (ops (i32 Default))> {
> + let PrintMethod = PM;
> +}
> +
> +def InstFlag : InstFlag;
> +def NEG : InstFlag <"printNeg">;
> +def ABS : InstFlag <"printAbs">;
>
> def COND_EQ : PatLeaf <
> (cond),
> diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
> index 0734cca..63f95f6 100644
> --- a/lib/Target/R600/R600Instructions.td
> +++ b/lib/Target/R600/R600Instructions.td
> @@ -31,11 +31,6 @@ def MEMrr : Operand<iPTR> {
>
> // Operands for non-registers
>
> -class InstFlag<string PM = "printOperand", int Default = 0>
> - : OperandWithDefaultOps <i32, (ops (i32 Default))> {
> - let PrintMethod = PM;
> -}
> -
> // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
> def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
> let PrintMethod = "printSel";
> @@ -50,8 +45,6 @@ def WRITE : InstFlag <"printWrite", 1>;
> def OMOD : InstFlag <"printOMOD">;
> def REL : InstFlag <"printRel">;
> def CLAMP : InstFlag <"printClamp">;
> -def NEG : InstFlag <"printNeg">;
> -def ABS : InstFlag <"printAbs">;
> def UEM : InstFlag <"printUpdateExecMask">;
> def UP : InstFlag <"printUpdatePred">;
>
> diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
> index 2c9270e..9f2e0e0 100644
> --- a/lib/Target/R600/SIISelLowering.cpp
> +++ b/lib/Target/R600/SIISelLowering.cpp
> @@ -326,10 +326,46 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
> .addReg(MI->getOperand(1).getReg())
> .addReg(MI->getOperand(2).getReg())
> .addImm(0) /* src2 */
> - .addImm(0) /* ABS */
> + .addImm(0) /* src0_abs */
> + .addImm(0) /* src1_abs */
> + .addImm(0) /* src2_abs */
> .addImm(0) /* CLAMP */
> .addImm(0) /* OMOD */
> - .addImm(2); /* NEG */
> + .addImm(0) /* src0_neg */
> + .addImm(1) /* src1_neg */
> + .addImm(0); /* src2_neg */
> + MI->eraseFromParent();
> + break;
> + }
> + case AMDGPU::FABS_SI: {
> + const SIInstrInfo *TII =
> + static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
> + BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64),
> + MI->getOperand(0).getReg())
> + .addReg(MI->getOperand(1).getReg())
> + .addImm(0) /* SRC1 */
> + .addImm(1) /* SRC0_ABS */
> + .addImm(0) /* SRC1_ABS */
> + .addImm(0) /* CLAMP */
> + .addImm(0) /* OMOD */
> + .addImm(0) /* SRC0_NEG */
> + .addImm(0); /* SRC1_NEG */
> + MI->eraseFromParent();
> + break;
> + }
> + case AMDGPU::FNEG_SI: {
> + const SIInstrInfo *TII =
> + static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
> + BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64),
> + MI->getOperand(0).getReg())
> + .addReg(MI->getOperand(1).getReg())
> + .addImm(0) /* SRC1 */
> + .addImm(0) /* SRC0_ABS */
> + .addImm(0) /* SRC1_ABS */
> + .addImm(0) /* CLAMP */
> + .addImm(0) /* OMOD */
> + .addImm(1) /* SRC0_NEG */
> + .addImm(0); /* SRC1_NEG */
> MI->eraseFromParent();
> break;
> }
> @@ -930,8 +966,9 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
> int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
> const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? 0 : &TII->get(OpcodeE64);
>
> + unsigned NumExtraOps = DescE64 ? DescE64->getNumOperands() - NumOps : 4;
> +
> assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
> - assert(!DescE64 || DescE64->getNumOperands() == (NumOps + 4));
>
> int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
> bool HaveVSrc = false, HaveSSrc = false;
> @@ -1031,7 +1068,7 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
>
> if (Promote2e64) {
> // Add the modifier flags while promoting
> - for (unsigned i = 0; i < 4; ++i)
> + for (unsigned i = 0; i < NumExtraOps; ++i)
> Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
> }
>
> diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td
> index 962e266..1bc94f7 100644
> --- a/lib/Target/R600/SIInstrFormats.td
> +++ b/lib/Target/R600/SIInstrFormats.td
> @@ -206,13 +206,19 @@ class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
> bits<9> src0;
> bits<9> src1;
> bits<9> src2;
> - bits<3> abs;
> + bits<1> src0_abs;
> + bits<1> src1_abs;
> + bits<1> src2_abs;
> bits<1> clamp;
> bits<2> omod;
> - bits<3> neg;
> + bits<1> src0_neg;
> + bits<1> src1_neg;
> + bits<1> src2_neg;
>
> let Inst{7-0} = dst;
> - let Inst{10-8} = abs;
> + let Inst{8} = src0_abs;
> + let Inst{9} = src1_abs;
> + let Inst{10} = src2_abs;
> let Inst{11} = clamp;
> let Inst{25-17} = op;
> let Inst{31-26} = 0x34; //encoding
> @@ -220,7 +226,9 @@ class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
> let Inst{49-41} = src1;
> let Inst{58-50} = src2;
> let Inst{60-59} = omod;
> - let Inst{63-61} = neg;
> + let Inst{61} = src0_neg;
> + let Inst{62} = src1_neg;
> + let Inst{63} = src2_neg;
>
> let mayLoad = 0;
> let mayStore = 0;
> @@ -238,7 +246,9 @@ class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
> bits<9> src2;
> bits<7> sdst;
> bits<2> omod;
> - bits<3> neg;
> + bits<1> src0_neg;
> + bits<1> src1_neg;
> + bits<1> src2_neg;
>
> let Inst{7-0} = dst;
> let Inst{14-8} = sdst;
> @@ -248,7 +258,9 @@ class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
> let Inst{49-41} = src1;
> let Inst{58-50} = src2;
> let Inst{60-59} = omod;
> - let Inst{63-61} = neg;
> + let Inst{61} = src0_neg;
> + let Inst{62} = src1_neg;
> + let Inst{63} = src2_neg;
>
> let mayLoad = 0;
> let mayStore = 0;
> diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
> index ed42a2a..3ed7533 100644
> --- a/lib/Target/R600/SIInstrInfo.td
> +++ b/lib/Target/R600/SIInstrInfo.td
> @@ -232,9 +232,9 @@ multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
> {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
> (outs drc:$dst),
> (ins src:$src0,
> - i32imm:$abs, i32imm:$clamp,
> - i32imm:$omod, i32imm:$neg),
> - opName#"_e64 $dst, $src0, $abs, $clamp, $omod, $neg", []
> + ABS:$src0_abs, i32imm:$clamp,
> + i32imm:$omod, NEG:$src0_neg),
> + opName#"_e64 $dst, $src0_neg$src0_abs$src0$src0_abs, $clamp, $omod", []
> >, VOP <opName> {
> let src1 = SIOperand.ZERO;
> let src2 = SIOperand.ZERO;
> @@ -264,11 +264,17 @@ multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
> {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
> (outs vrc:$dst),
> (ins arc:$src0, arc:$src1,
> - i32imm:$abs, i32imm:$clamp,
> - i32imm:$omod, i32imm:$neg),
> - opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
> + ABS:$src0_abs, ABS:$src1_abs,
> + i32imm:$clamp, i32imm:$omod,
> + NEG:$src0_neg, NEG:$src1_neg),
> + opName#"_e64 $dst, $src0_neg$src0_abs$src0$src0_abs, "
> + "$src1_neg$src1_abs$src1$src1_abs, $clamp, $omod", []
> >, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
> let src2 = SIOperand.ZERO;
> + let src1_neg = 0;
> + let src2_neg = 0;
> + let src1_abs = 0;
> + let src2_abs = 0;
> }
> }
>
> @@ -292,15 +298,18 @@ multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern,
> {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
> (outs VReg_32:$dst),
> (ins VSrc_32:$src0, VSrc_32:$src1,
> - i32imm:$abs, i32imm:$clamp,
> - i32imm:$omod, i32imm:$neg),
> - opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
> + ABS:$src0_abs, ABS:$src1_abs, i32imm:$clamp,
> + i32imm:$omod, NEG:$src0_neg, NEG:$src1_neg),
> + opName#"_e64 $dst, $src0_neg$src0_abs$src0$src0_abs, "
> + "$src1_neg$src1_abs$src1$src1_abs, $clamp, $omod", []
> >, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
> let src2 = SIOperand.ZERO;
> /* the VOP2 variant puts the carry out into VCC, the VOP3 variant
> can write it into any SGPR. We currently don't use the carry out,
> so for now hardcode it to VCC as well */
> let sdst = SIOperand.VCC;
> +
> + let src2_neg = 0;
> }
> }
>
> @@ -316,14 +325,17 @@ multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
> {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
> (outs SReg_64:$dst),
> (ins arc:$src0, arc:$src1,
> - InstFlag:$abs, InstFlag:$clamp,
> - InstFlag:$omod, InstFlag:$neg),
> - opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg",
> + ABS:$src0_abs, ABS:$src1_abs, InstFlag:$clamp,
> + InstFlag:$omod, NEG:$src0_neg, NEG:$src1_neg),
> + opName#"_e64 $dst, $src0_neg$src0_abs$src0$src0_abs, "
> + "$src1_neg$src1_abs$src1$src1_abs, $clamp, $omod",
> !if(!eq(!cast<string>(cond), "COND_NULL"), []<dag>,
> [(set SReg_64:$dst, (i1 (setcc (vt arc:$src0), arc:$src1, cond)))]
> )
> >, VOP <opName> {
> let src2 = SIOperand.ZERO;
> + let src2_abs = 0;
> + let src2_neg = 0;
> }
> }
>
> @@ -338,8 +350,11 @@ multiclass VOPC_64 <bits<8> op, string opName,
> class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
> op, (outs VReg_32:$dst),
> (ins VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2,
> - InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
> - opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
> + ABS:$src0_abs, ABS:$src1_abs, ABS:$src2_abs, InstFlag:$clamp, InstFlag:$omod,
> + NEG:$src0_neg, NEG:$src1_neg, NEG:$src2_neg),
> + opName#" $dst, $src0_neg$src0_abs$src0$src0_abs, "
> + "$src1_neg$src1_abs$src1$src1_abs, "
> + "$src2_neg$src2_abs$src2$src2_abs, $clamp, $omod", pattern
> >, VOP <opName>;
>
> class VOP3_64_Shift <bits <9> op, string opName, list<dag> pattern> : VOP3 <
> @@ -349,17 +364,25 @@ class VOP3_64_Shift <bits <9> op, string opName, list<dag> pattern> : VOP3 <
> >, VOP <opName> {
>
> let src2 = SIOperand.ZERO;
> - let abs = 0;
> + let src0_abs = 0;
> + let src1_abs = 0;
> + let src2_abs = 0;
> let clamp = 0;
> let omod = 0;
> - let neg = 0;
> + let src0_neg = 0;
> + let src1_neg = 0;
> + let src2_neg = 0;
> }
>
> class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
> op, (outs VReg_64:$dst),
> (ins VSrc_64:$src0, VSrc_64:$src1, VSrc_64:$src2,
> - InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
> - opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
> + ABS:$src0_abs, ABS:$src1_abs, ABS:$src2_abs,
> + InstFlag:$clamp, InstFlag:$omod,
> + NEG:$src0_neg, NEG:$src1_neg, NEG:$src2_neg),
> + opName#" $dst, $src0_neg$src0_abs$src0$src0_abs, "
> + "$src1_neg$src1_abs$src1$src1_abs, "
> + "$src2_neg$src2_abs$src2$src2_abs, $clamp, $omod", pattern
> >, VOP <opName>;
>
> //===----------------------------------------------------------------------===//
> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> index 94d42d5..525ab19 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -842,8 +842,12 @@ def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
>
> def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
> (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2,
> - InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
> - "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
> + ABS:$src0_abs, ABS:$src1_abs, ABS:$src2_abs,
> + InstFlag:$clamp, InstFlag:$omod,
> + NEG:$src0_neg, NEG:$src1_neg, NEG:$src2_neg),
> + "V_CNDMASK_B32_e64 $dst, $src0_neg$src0_abs$src0$src0_abs, "
> + "$src1_neg$src1_abs$src1$src1_abs, "
> + "$src2_neg$src2_abs$src2$src2_abs, $clamp, $omod",
> [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
> >;
>
> @@ -1576,20 +1580,12 @@ def : BitConvert <v32i8, v8i32, VReg_256>;
> def : Pat <
> (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
> (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
> - 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
> + 1 /* CLAMP */, 0 /* OMOD */)
> >;
>
> -def : Pat <
> - (fabs f32:$src),
> - (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
> - 1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
> ->;
> +def FNEG_SI : FNEG<VSrc_32>;
> +def FABS_SI : FABS<VSrc_32>;
>
> -def : Pat <
> - (fneg f32:$src),
> - (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
> - 0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */)
> ->;
>
> /********** ================== **********/
> /********** Immediate Patterns **********/
> @@ -1744,7 +1740,7 @@ def : Pat <
> def : Pat <
> (int_SI_tid),
> (V_MBCNT_HI_U32_B32_e32 0xffffffff,
> - (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0, 0, 0))
> + (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0))
> >;
>
> /********** ================== **********/
> diff --git a/test/CodeGen/R600/fabs.ll b/test/CodeGen/R600/fabs.ll
> index d318c42..32c5605 100644
> --- a/test/CodeGen/R600/fabs.ll
> +++ b/test/CodeGen/R600/fabs.ll
> @@ -9,7 +9,7 @@
> ; R600-CHECK-NOT: AND
> ; R600-CHECK: |PV.{{[XYZW]}}|
> ; SI-CHECK: @fabs_free
> -; SI-CHECK: V_ADD_F32_e64 VGPR{{[0-9]}}, SGPR{{[0-9]}}, 0, 1, 0, 0, 0
> +; SI-CHECK: V_ADD_F32_e64 VGPR{{[0-9]}}, |SGPR{{[0-9]}}|, 0, 0, 0
>
> define void @fabs_free(float addrspace(1)* %out, i32 %in) {
> entry:
> diff --git a/test/CodeGen/R600/fneg.ll b/test/CodeGen/R600/fneg.ll
> index f7083cd..3932668 100644
> --- a/test/CodeGen/R600/fneg.ll
> +++ b/test/CodeGen/R600/fneg.ll
> @@ -1,8 +1,11 @@
> -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
> +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
> +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
>
> -; CHECK: @fneg_v2
> -; CHECK: -PV
> -; CHECK: -PV
> +; R600-CHECK-LABEL: @fneg_v2
> +; R600-CHECK: -PV
> +; R600-CHECK: -PV
> +; SI-CHECK-LABEL: @fneg_v2
> +; SI-CHECK: V_ADD_F32_e64 VGPR{{[0-9]}}, -SGPR{{[0-9]}}
> define void @fneg_v2(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
> entry:
> %0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
> @@ -10,11 +13,13 @@ entry:
> ret void
> }
>
> -; CHECK: @fneg_v4
> -; CHECK: -PV
> -; CHECK: -T
> -; CHECK: -PV
> -; CHECK: -PV
> +; R600-CHECK-LABEL: @fneg_v4
> +; R600-CHECK: -PV
> +; R600-CHECK: -T
> +; R600-CHECK: -PV
> +; R600-CHECK: -PV
> +; SI-CHECK-LABEL: @fneg_v4
> +; SI-CHECK: V_ADD_F32_e64 VGPR{{[0-9]}}, -VGPR{{[0-9]}}
> define void @fneg_v4(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
> entry:
> %0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
> diff --git a/test/CodeGen/R600/fsub64.ll b/test/CodeGen/R600/fsub64.ll
> index 56c5c0c..9c51947 100644
> --- a/test/CodeGen/R600/fsub64.ll
> +++ b/test/CodeGen/R600/fsub64.ll
> @@ -1,7 +1,7 @@
> ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s
>
> ; CHECK: @fsub_f64
> -; CHECK: V_ADD_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}, 0, 0, 0, 0, 2
> +; CHECK: V_ADD_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, -VGPR[0-9]+_VGPR[0-9]+}}, 0, 0
>
> define void @fsub_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
> double addrspace(1)* %in2) {
> diff --git a/test/CodeGen/R600/seto.ll b/test/CodeGen/R600/seto.ll
> index 72007e6..0bc9b0b 100644
> --- a/test/CodeGen/R600/seto.ll
> +++ b/test/CodeGen/R600/seto.ll
> @@ -1,6 +1,6 @@
> ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
>
> -;CHECK: V_CMP_O_F32_e64 SGPR0_SGPR1, {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}, 0, 0, 0, 0
> +;CHECK: V_CMP_O_F32_e64 SGPR0_SGPR1, {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}, 0, 0
>
> define void @main(float %p) {
> main_body:
> diff --git a/test/CodeGen/R600/setuo.ll b/test/CodeGen/R600/setuo.ll
> index a9cadfa..c45e7a2 100644
> --- a/test/CodeGen/R600/setuo.ll
> +++ b/test/CodeGen/R600/setuo.ll
> @@ -1,6 +1,6 @@
> ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
>
> -;CHECK: V_CMP_U_F32_e64 SGPR0_SGPR1, {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}, 0, 0, 0, 0
> +;CHECK: V_CMP_U_F32_e64 SGPR0_SGPR1, {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}, 0, 0
>
> define void @main(float %p) {
> main_body:
> --
> 1.8.3.1
>
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