[PATCH] sra->srl reduction and PowerPC test change

[Richard Sandiford]

SimplifyDemandedBits has code to turn sra into srl if the shifted-in
sign bits don't matter.  This makes it easier to combine the shift with
others (such as a shift left).

The attached patch extends this to cases where the only bit that matters
is a sign bit.  E.g. (and (sra (i32 x) 31) 2) -> (and (srl (i32 x) 30) 2).

I think the codegen part is obvious enough to just apply (but please let
me know if I'm wrong).  However, the optimisation changes the output of
test/CodeGen/PowerPC/rlwimi-and.ll.  The old code was:

        li 3, 0
        lbz 12, 0(3)
        cmplwi 0, 3, 0
        slwi 4, 12, 31
        rlwinm 3, 12, 0, 31, 31
        srawi 4, 4, 31
        rlwinm 4, 4, 0, 23, 23
        rlwimi 4, 3, 0, 24, 22
        sth 4, 0(3)

The new code is:

        li 3, 0
        lbz 12, 0(3)
        cmplwi 0, 3, 0
        slwi 4, 12, 31
        rlwinm 3, 12, 0, 31, 31
        rlwimi 3, 4, 9, 23, 23
        sth 3, 0(3)

Is the test change OK?  As mentioned in the FIXME, I think we could also
fold the SLWI into the RLWIMI, but that'd probably be a back-end change.

Thanks,
Richard

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