[llvm] r192622 - Use a SparseSet in LiveRegUnits.
Andrew Trick
atrick at apple.com
Mon Oct 14 13:45:17 PDT 2013
Author: atrick
Date: Mon Oct 14 15:45:17 2013
New Revision: 192622
URL: http://llvm.org/viewvc/llvm-project?rev=192622&view=rev
Log:
Use a SparseSet in LiveRegUnits.
Some clients may add block live ins and may track liveness over a
large scope. This guarantees an efficient implementation in all cases
with no memory allocation/deallocation, independent of the number of
target registers. It could be slightly less convenient but is fine in
the expected case.
Modified:
llvm/trunk/include/llvm/CodeGen/LiveRegUnits.h
llvm/trunk/lib/CodeGen/IfConversion.cpp
Modified: llvm/trunk/include/llvm/CodeGen/LiveRegUnits.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveRegUnits.h?rev=192622&r1=192621&r2=192622&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveRegUnits.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveRegUnits.h Mon Oct 14 15:45:17 2013
@@ -17,9 +17,9 @@
#ifndef LLVM_CODEGEN_LIVEREGUNITS_H
#define LLVM_CODEGEN_LIVEREGUNITS_H
-#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/SparseSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
namespace llvm {
@@ -29,17 +29,23 @@ class MachineInstr;
/// A set of live register units with functions to track liveness when walking
/// backward/forward through a basic block.
class LiveRegUnits {
- SmallSet<unsigned, 32> LiveUnits;
+ SparseSet<unsigned> LiveUnits;
+ LiveRegUnits(const LiveRegUnits&) LLVM_DELETED_FUNCTION;
+ LiveRegUnits &operator=(const LiveRegUnits&) LLVM_DELETED_FUNCTION;
public:
/// \brief Constructs a new empty LiveRegUnits set.
LiveRegUnits() {}
- /// \brief Constructs a new LiveRegUnits set by copying @p Other.
- LiveRegUnits(const LiveRegUnits &Other)
- : LiveUnits(Other.LiveUnits) {
+ void init(const TargetRegisterInfo *TRI) {
+ LiveUnits.clear();
+ LiveUnits.setUniverse(TRI->getNumRegs());
}
+ void clear() { LiveUnits.clear(); }
+
+ bool empty() const { return LiveUnits.empty(); }
+
/// \brief Adds a register to the set.
void addReg(unsigned Reg, const MCRegisterInfo &MCRI) {
for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits)
@@ -73,7 +79,7 @@ public:
/// instruction(bundle): Remove killed-uses, add defs.
void stepForward(const MachineInstr &MI, const MCRegisterInfo &MCRI);
- /// Adds all registers in the live-in list of block @p BB.
+ /// \brief Adds all registers in the live-in list of block @p BB.
void addLiveIns(const MachineBasicBlock &BB, const MCRegisterInfo &MCRI);
};
Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=192622&r1=192621&r2=192622&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/IfConversion.cpp Mon Oct 14 15:45:17 2013
@@ -162,6 +162,9 @@ namespace {
const MachineBranchProbabilityInfo *MBPI;
MachineRegisterInfo *MRI;
+ LiveRegUnits Redefs;
+ LiveRegUnits DontKill;
+
bool PreRegAlloc;
bool MadeChange;
int FnNum;
@@ -202,12 +205,9 @@ namespace {
void PredicateBlock(BBInfo &BBI,
MachineBasicBlock::iterator E,
SmallVectorImpl<MachineOperand> &Cond,
- LiveRegUnits &Redefs,
SmallSet<unsigned, 4> *LaterRedefs = 0);
void CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
SmallVectorImpl<MachineOperand> &Cond,
- LiveRegUnits &Redefs,
- const LiveRegUnits *DontKill = 0,
bool IgnoreBr = false);
void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges = true);
@@ -1048,27 +1048,27 @@ bool IfConverter::IfConvertSimple(BBInfo
// Initialize liveins to the first BB. These are potentiall redefined by
// predicated instructions.
- LiveRegUnits Redefs;
+ Redefs.init(TRI);
Redefs.addLiveIns(*(CvtBBI->BB), *TRI);
Redefs.addLiveIns(*(NextBBI->BB), *TRI);
// Compute a set of registers which must not be killed by instructions in
// BB1: This is everything live-in to BB2.
- LiveRegUnits DontKill;
+ DontKill.init(TRI);
DontKill.addLiveIns(*(NextBBI->BB), *TRI);
if (CvtBBI->BB->pred_size() > 1) {
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
// Copy instructions in the true block, predicate them, and add them to
// the entry block.
- CopyAndPredicateBlock(BBI, *CvtBBI, Cond, Redefs, &DontKill);
+ CopyAndPredicateBlock(BBI, *CvtBBI, Cond);
// RemoveExtraEdges won't work if the block has an unanalyzable branch, so
// explicitly remove CvtBBI as a successor.
BBI.BB->removeSuccessor(CvtBBI->BB);
} else {
RemoveKills(CvtBBI->BB->begin(), CvtBBI->BB->end(), DontKill, *TRI);
- PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond, Redefs);
+ PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond);
// Merge converted block into entry block.
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
@@ -1153,16 +1153,18 @@ bool IfConverter::IfConvertTriangle(BBIn
// Initialize liveins to the first BB. These are potentially redefined by
// predicated instructions.
- LiveRegUnits Redefs;
+ Redefs.init(TRI);
Redefs.addLiveIns(*(CvtBBI->BB), *TRI);
Redefs.addLiveIns(*(NextBBI->BB), *TRI);
+ DontKill.clear();
+
bool HasEarlyExit = CvtBBI->FalseBB != NULL;
if (CvtBBI->BB->pred_size() > 1) {
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
// Copy instructions in the true block, predicate them, and add them to
// the entry block.
- CopyAndPredicateBlock(BBI, *CvtBBI, Cond, Redefs, 0, true);
+ CopyAndPredicateBlock(BBI, *CvtBBI, Cond, true);
// RemoveExtraEdges won't work if the block has an unanalyzable branch, so
// explicitly remove CvtBBI as a successor.
@@ -1170,7 +1172,7 @@ bool IfConverter::IfConvertTriangle(BBIn
} else {
// Predicate the 'true' block after removing its branch.
CvtBBI->NonPredSize -= TII->RemoveBranch(*CvtBBI->BB);
- PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond, Redefs);
+ PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond);
// Now merge the entry of the triangle with the true block.
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
@@ -1281,7 +1283,7 @@ bool IfConverter::IfConvertDiamond(BBInf
// Initialize liveins to the first BB. These are potentially redefined by
// predicated instructions.
- LiveRegUnits Redefs;
+ Redefs.init(TRI);
Redefs.addLiveIns(*(BBI1->BB), *TRI);
// Remove the duplicated instructions at the beginnings of both paths.
@@ -1312,7 +1314,7 @@ bool IfConverter::IfConvertDiamond(BBInf
// Compute a set of registers which must not be killed by instructions in BB1:
// This is everything used+live in BB2 after the duplicated instructions. We
// can compute this set by simulating liveness backwards from the end of BB2.
- LiveRegUnits DontKill;
+ DontKill.init(TRI);
for (MachineBasicBlock::reverse_iterator I = BBI2->BB->rbegin(),
E = MachineBasicBlock::reverse_iterator(DI2); I != E; ++I) {
DontKill.stepBackward(*I, *TRI);
@@ -1401,10 +1403,10 @@ bool IfConverter::IfConvertDiamond(BBInf
}
// Predicate the 'true' block.
- PredicateBlock(*BBI1, BBI1->BB->end(), *Cond1, Redefs, &RedefsByFalse);
+ PredicateBlock(*BBI1, BBI1->BB->end(), *Cond1, &RedefsByFalse);
// Predicate the 'false' block.
- PredicateBlock(*BBI2, DI2, *Cond2, Redefs);
+ PredicateBlock(*BBI2, DI2, *Cond2);
// Merge the true block into the entry of the diamond.
MergeBlocks(BBI, *BBI1, TailBB == 0);
@@ -1479,7 +1481,6 @@ static bool MaySpeculate(const MachineIn
void IfConverter::PredicateBlock(BBInfo &BBI,
MachineBasicBlock::iterator E,
SmallVectorImpl<MachineOperand> &Cond,
- LiveRegUnits &Redefs,
SmallSet<unsigned, 4> *LaterRedefs) {
bool AnyUnpred = false;
bool MaySpec = LaterRedefs != 0;
@@ -1522,8 +1523,6 @@ void IfConverter::PredicateBlock(BBInfo
/// the destination block. Skip end of block branches if IgnoreBr is true.
void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
SmallVectorImpl<MachineOperand> &Cond,
- LiveRegUnits &Redefs,
- const LiveRegUnits *DontKill,
bool IgnoreBr) {
MachineFunction &MF = *ToBBI.BB->getParent();
@@ -1556,8 +1555,8 @@ void IfConverter::CopyAndPredicateBlock(
UpdatePredRedefs(MI, Redefs, TRI);
// Some kill flags may not be correct anymore.
- if (DontKill != 0)
- RemoveKills(*MI, *DontKill, *TRI);
+ if (!DontKill.empty())
+ RemoveKills(*MI, DontKill, *TRI);
}
if (!IgnoreBr) {
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