[llvm] r192589 - [mips][msa] Direct Object Emission support for BIT instructions.
Matheus Almeida
matheus.almeida at imgtec.com
Mon Oct 14 06:07:39 PDT 2013
Author: matheusalmeida
Date: Mon Oct 14 08:07:39 2013
New Revision: 192589
URL: http://llvm.org/viewvc/llvm-project?rev=192589&view=rev
Log:
[mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}
Added:
llvm/trunk/test/MC/Mips/msa/test_bit.s
Modified:
llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td?rev=192589&r1=192588&r2=192589&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td Mon Oct 14 08:07:39 2013
@@ -22,26 +22,54 @@ class PseudoMSA<dag outs, dag ins, list<
}
class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
+ bits<5> ws;
+ bits<5> wd;
+ bits<3> m;
+
let Inst{25-23} = major;
let Inst{22-19} = 0b1110;
+ let Inst{18-16} = m;
+ let Inst{15-11} = ws;
+ let Inst{10-6} = wd;
let Inst{5-0} = minor;
}
class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
+ bits<5> ws;
+ bits<5> wd;
+ bits<4> m;
+
let Inst{25-23} = major;
let Inst{22-20} = 0b110;
+ let Inst{19-16} = m;
+ let Inst{15-11} = ws;
+ let Inst{10-6} = wd;
let Inst{5-0} = minor;
}
class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
+ bits<5> ws;
+ bits<5> wd;
+ bits<5> m;
+
let Inst{25-23} = major;
let Inst{22-21} = 0b10;
+ let Inst{20-16} = m;
+ let Inst{15-11} = ws;
+ let Inst{10-6} = wd;
let Inst{5-0} = minor;
}
class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
+ bits<5> ws;
+ bits<5> wd;
+ bits<6> m;
+
let Inst{25-23} = major;
let Inst{22} = 0b0;
+ let Inst{21-16} = m;
+ let Inst{15-11} = ws;
+ let Inst{10-6} = wd;
let Inst{5-0} = minor;
}
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td?rev=192589&r1=192588&r2=192589&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td Mon Oct 14 08:07:39 2013
@@ -1025,53 +1025,53 @@ class XORI_B_ENC : MSA_I8_FMT<0b11, 0b00
// Instruction desc.
class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- RegisterClass RCWD, RegisterClass RCWS = RCWD,
+ RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
- dag OutOperandList = (outs RCWD:$wd);
- dag InOperandList = (ins RCWS:$ws, uimm3:$u3);
- string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u3");
- list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, immZExt3:$u3))];
+ dag OutOperandList = (outs ROWD:$wd);
+ dag InOperandList = (ins ROWS:$ws, uimm3:$m);
+ string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
+ list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))];
InstrItinClass Itinerary = itin;
}
class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- RegisterClass RCWD, RegisterClass RCWS = RCWD,
+ RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
- dag OutOperandList = (outs RCWD:$wd);
- dag InOperandList = (ins RCWS:$ws, uimm4:$u4);
- string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u4");
- list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, immZExt4:$u4))];
+ dag OutOperandList = (outs ROWD:$wd);
+ dag InOperandList = (ins ROWS:$ws, uimm4:$m);
+ string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
+ list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))];
InstrItinClass Itinerary = itin;
}
class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- RegisterClass RCWD, RegisterClass RCWS = RCWD,
+ RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
- dag OutOperandList = (outs RCWD:$wd);
- dag InOperandList = (ins RCWS:$ws, uimm5:$u5);
- string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u5");
- list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, immZExt5:$u5))];
+ dag OutOperandList = (outs ROWD:$wd);
+ dag InOperandList = (ins ROWS:$ws, uimm5:$m);
+ string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
+ list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))];
InstrItinClass Itinerary = itin;
}
class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- RegisterClass RCWD, RegisterClass RCWS = RCWD,
+ RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
- dag OutOperandList = (outs RCWD:$wd);
- dag InOperandList = (ins RCWS:$ws, uimm6:$u6);
- string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u6");
- list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, immZExt6:$u6))];
+ dag OutOperandList = (outs ROWD:$wd);
+ dag InOperandList = (ins ROWS:$ws, uimm6:$m);
+ string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
+ list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))];
InstrItinClass Itinerary = itin;
}
class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- SplatComplexPattern SplatImm, RegisterClass RCWD,
- RegisterClass RCWS = RCWD,
+ SplatComplexPattern SplatImm,
+ RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
- dag OutOperandList = (outs RCWD:$wd);
- dag InOperandList = (ins RCWS:$ws, SplatImm.OpClass:$u);
- string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u");
- list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, SplatImm:$u))];
+ dag OutOperandList = (outs ROWD:$wd);
+ dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
+ string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
+ list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
InstrItinClass Itinerary = itin;
}
@@ -1430,10 +1430,14 @@ class BCLR_H_DESC : MSA_3R_DESC_BASE<"bc
class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", int_mips_bclr_w, MSA128WOpnd>;
class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", int_mips_bclr_d, MSA128DOpnd>;
-class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", int_mips_bclri_b, MSA128B>;
-class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", int_mips_bclri_h, MSA128H>;
-class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", int_mips_bclri_w, MSA128W>;
-class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", int_mips_bclri_d, MSA128D>;
+class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", int_mips_bclri_b,
+ MSA128BOpnd>;
+class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", int_mips_bclri_h,
+ MSA128HOpnd>;
+class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", int_mips_bclri_w,
+ MSA128WOpnd>;
+class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", int_mips_bclri_d,
+ MSA128DOpnd>;
class BINSL_B_DESC : MSA_3R_DESC_BASE<"binsl.b", int_mips_binsl_b, MSA128BOpnd>;
class BINSL_H_DESC : MSA_3R_DESC_BASE<"binsl.h", int_mips_binsl_h, MSA128HOpnd>;
@@ -1441,13 +1445,13 @@ class BINSL_W_DESC : MSA_3R_DESC_BASE<"b
class BINSL_D_DESC : MSA_3R_DESC_BASE<"binsl.d", int_mips_binsl_d, MSA128DOpnd>;
class BINSLI_B_DESC : MSA_BIT_B_DESC_BASE<"binsli.b", int_mips_binsli_b,
- MSA128B>;
+ MSA128BOpnd>;
class BINSLI_H_DESC : MSA_BIT_H_DESC_BASE<"binsli.h", int_mips_binsli_h,
- MSA128H>;
+ MSA128HOpnd>;
class BINSLI_W_DESC : MSA_BIT_W_DESC_BASE<"binsli.w", int_mips_binsli_w,
- MSA128W>;
+ MSA128WOpnd>;
class BINSLI_D_DESC : MSA_BIT_D_DESC_BASE<"binsli.d", int_mips_binsli_d,
- MSA128D>;
+ MSA128DOpnd>;
class BINSR_B_DESC : MSA_3R_DESC_BASE<"binsr.b", int_mips_binsr_b, MSA128BOpnd>;
class BINSR_H_DESC : MSA_3R_DESC_BASE<"binsr.h", int_mips_binsr_h, MSA128HOpnd>;
@@ -1455,13 +1459,13 @@ class BINSR_W_DESC : MSA_3R_DESC_BASE<"b
class BINSR_D_DESC : MSA_3R_DESC_BASE<"binsr.d", int_mips_binsr_d, MSA128DOpnd>;
class BINSRI_B_DESC : MSA_BIT_B_DESC_BASE<"binsri.b", int_mips_binsri_b,
- MSA128B>;
+ MSA128BOpnd>;
class BINSRI_H_DESC : MSA_BIT_H_DESC_BASE<"binsri.h", int_mips_binsri_h,
- MSA128H>;
+ MSA128HOpnd>;
class BINSRI_W_DESC : MSA_BIT_W_DESC_BASE<"binsri.w", int_mips_binsri_w,
- MSA128W>;
+ MSA128WOpnd>;
class BINSRI_D_DESC : MSA_BIT_D_DESC_BASE<"binsri.d", int_mips_binsri_d,
- MSA128D>;
+ MSA128DOpnd>;
class BMNZ_V_DESC : MSA_VEC_DESC_BASE<"bmnz.v", int_mips_bmnz_v, MSA128BOpnd>;
@@ -1477,10 +1481,14 @@ class BNEG_H_DESC : MSA_3R_DESC_BASE<"bn
class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", int_mips_bneg_w, MSA128WOpnd>;
class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", int_mips_bneg_d, MSA128DOpnd>;
-class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", int_mips_bnegi_b, MSA128B>;
-class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", int_mips_bnegi_h, MSA128H>;
-class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", int_mips_bnegi_w, MSA128W>;
-class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", int_mips_bnegi_d, MSA128D>;
+class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", int_mips_bnegi_b,
+ MSA128BOpnd>;
+class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", int_mips_bnegi_h,
+ MSA128HOpnd>;
+class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", int_mips_bnegi_w,
+ MSA128WOpnd>;
+class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", int_mips_bnegi_d,
+ MSA128DOpnd>;
class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128B>;
class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128H>;
@@ -1518,10 +1526,14 @@ class BSET_H_DESC : MSA_3R_DESC_BASE<"bs
class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", int_mips_bset_w, MSA128WOpnd>;
class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", int_mips_bset_d, MSA128DOpnd>;
-class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", int_mips_bseti_b, MSA128B>;
-class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", int_mips_bseti_h, MSA128H>;
-class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", int_mips_bseti_w, MSA128W>;
-class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", int_mips_bseti_d, MSA128D>;
+class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", int_mips_bseti_b,
+ MSA128BOpnd>;
+class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", int_mips_bseti_h,
+ MSA128HOpnd>;
+class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", int_mips_bseti_w,
+ MSA128WOpnd>;
+class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", int_mips_bseti_d,
+ MSA128DOpnd>;
class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128B>;
class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128H>;
@@ -2204,15 +2216,23 @@ class PCNT_H_DESC : MSA_2R_DESC_BASE<"pc
class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
-class SAT_S_B_DESC : MSA_BIT_B_DESC_BASE<"sat_s.b", int_mips_sat_s_b, MSA128B>;
-class SAT_S_H_DESC : MSA_BIT_H_DESC_BASE<"sat_s.h", int_mips_sat_s_h, MSA128H>;
-class SAT_S_W_DESC : MSA_BIT_W_DESC_BASE<"sat_s.w", int_mips_sat_s_w, MSA128W>;
-class SAT_S_D_DESC : MSA_BIT_D_DESC_BASE<"sat_s.d", int_mips_sat_s_d, MSA128D>;
-
-class SAT_U_B_DESC : MSA_BIT_B_DESC_BASE<"sat_u.b", int_mips_sat_u_b, MSA128B>;
-class SAT_U_H_DESC : MSA_BIT_H_DESC_BASE<"sat_u.h", int_mips_sat_u_h, MSA128H>;
-class SAT_U_W_DESC : MSA_BIT_W_DESC_BASE<"sat_u.w", int_mips_sat_u_w, MSA128W>;
-class SAT_U_D_DESC : MSA_BIT_D_DESC_BASE<"sat_u.d", int_mips_sat_u_d, MSA128D>;
+class SAT_S_B_DESC : MSA_BIT_B_DESC_BASE<"sat_s.b", int_mips_sat_s_b,
+ MSA128BOpnd>;
+class SAT_S_H_DESC : MSA_BIT_H_DESC_BASE<"sat_s.h", int_mips_sat_s_h,
+ MSA128HOpnd>;
+class SAT_S_W_DESC : MSA_BIT_W_DESC_BASE<"sat_s.w", int_mips_sat_s_w,
+ MSA128WOpnd>;
+class SAT_S_D_DESC : MSA_BIT_D_DESC_BASE<"sat_s.d", int_mips_sat_s_d,
+ MSA128DOpnd>;
+
+class SAT_U_B_DESC : MSA_BIT_B_DESC_BASE<"sat_u.b", int_mips_sat_u_b,
+ MSA128BOpnd>;
+class SAT_U_H_DESC : MSA_BIT_H_DESC_BASE<"sat_u.h", int_mips_sat_u_h,
+ MSA128HOpnd>;
+class SAT_U_W_DESC : MSA_BIT_W_DESC_BASE<"sat_u.w", int_mips_sat_u_w,
+ MSA128WOpnd>;
+class SAT_U_D_DESC : MSA_BIT_D_DESC_BASE<"sat_u.d", int_mips_sat_u_d,
+ MSA128DOpnd>;
class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
@@ -2234,13 +2254,13 @@ class SLL_W_DESC : MSA_3R_DESC_BASE<"sll
class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
- MSA128B>;
+ MSA128BOpnd>;
class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
- MSA128H>;
+ MSA128HOpnd>;
class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
- MSA128W>;
+ MSA128WOpnd>;
class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
- MSA128D>;
+ MSA128DOpnd>;
class SPLAT_B_DESC : MSA_3R_DESC_BASE<"splat.b", int_mips_splat_b, MSA128BOpnd,
MSA128BOpnd, GPR32Opnd>;
@@ -2266,23 +2286,27 @@ class SRA_W_DESC : MSA_3R_DESC_BASE<"sra
class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
- MSA128B>;
+ MSA128BOpnd>;
class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
- MSA128H>;
+ MSA128HOpnd>;
class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
- MSA128W>;
+ MSA128WOpnd>;
class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
- MSA128D>;
+ MSA128DOpnd>;
class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
-class SRARI_B_DESC : MSA_BIT_B_DESC_BASE<"srari.b", int_mips_srari_b, MSA128B>;
-class SRARI_H_DESC : MSA_BIT_H_DESC_BASE<"srari.h", int_mips_srari_h, MSA128H>;
-class SRARI_W_DESC : MSA_BIT_W_DESC_BASE<"srari.w", int_mips_srari_w, MSA128W>;
-class SRARI_D_DESC : MSA_BIT_D_DESC_BASE<"srari.d", int_mips_srari_d, MSA128D>;
+class SRARI_B_DESC : MSA_BIT_B_DESC_BASE<"srari.b", int_mips_srari_b,
+ MSA128BOpnd>;
+class SRARI_H_DESC : MSA_BIT_H_DESC_BASE<"srari.h", int_mips_srari_h,
+ MSA128HOpnd>;
+class SRARI_W_DESC : MSA_BIT_W_DESC_BASE<"srari.w", int_mips_srari_w,
+ MSA128WOpnd>;
+class SRARI_D_DESC : MSA_BIT_D_DESC_BASE<"srari.d", int_mips_srari_d,
+ MSA128DOpnd>;
class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
@@ -2290,23 +2314,27 @@ class SRL_W_DESC : MSA_3R_DESC_BASE<"srl
class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
- MSA128B>;
+ MSA128BOpnd>;
class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
- MSA128H>;
+ MSA128HOpnd>;
class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
- MSA128W>;
+ MSA128WOpnd>;
class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
- MSA128D>;
+ MSA128DOpnd>;
class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
-class SRLRI_B_DESC : MSA_BIT_B_DESC_BASE<"srlri.b", int_mips_srlri_b, MSA128B>;
-class SRLRI_H_DESC : MSA_BIT_H_DESC_BASE<"srlri.h", int_mips_srlri_h, MSA128H>;
-class SRLRI_W_DESC : MSA_BIT_W_DESC_BASE<"srlri.w", int_mips_srlri_w, MSA128W>;
-class SRLRI_D_DESC : MSA_BIT_D_DESC_BASE<"srlri.d", int_mips_srlri_d, MSA128D>;
+class SRLRI_B_DESC : MSA_BIT_B_DESC_BASE<"srlri.b", int_mips_srlri_b,
+ MSA128BOpnd>;
+class SRLRI_H_DESC : MSA_BIT_H_DESC_BASE<"srlri.h", int_mips_srlri_h,
+ MSA128HOpnd>;
+class SRLRI_W_DESC : MSA_BIT_W_DESC_BASE<"srlri.w", int_mips_srlri_w,
+ MSA128WOpnd>;
+class SRLRI_D_DESC : MSA_BIT_D_DESC_BASE<"srlri.d", int_mips_srlri_d,
+ MSA128DOpnd>;
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterClass RCWD, Operand MemOpnd = mem,
Added: llvm/trunk/test/MC/Mips/msa/test_bit.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/msa/test_bit.s?rev=192589&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/msa/test_bit.s (added)
+++ llvm/trunk/test/MC/Mips/msa/test_bit.s Mon Oct 14 08:07:39 2013
@@ -0,0 +1,150 @@
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 -mattr=+msa -arch=mips | FileCheck %s
+#
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+msa -arch=mips -filetype=obj -o - | llvm-objdump -d -triple=mipsel-unknown-linux -mattr=+msa -arch=mips - | FileCheck %s -check-prefix=CHECKOBJDUMP
+#
+# CHECK: bclri.b $w21, $w30, 2 # encoding: [0x79,0xf2,0xf5,0x49]
+# CHECK: bclri.h $w24, $w21, 0 # encoding: [0x79,0xe0,0xae,0x09]
+# CHECK: bclri.w $w23, $w30, 3 # encoding: [0x79,0xc3,0xf5,0xc9]
+# CHECK: bclri.d $w9, $w11, 0 # encoding: [0x79,0x80,0x5a,0x49]
+# CHECK: binsli.b $w25, $w12, 1 # encoding: [0x7b,0x71,0x66,0x49]
+# CHECK: binsli.h $w21, $w22, 0 # encoding: [0x7b,0x60,0xb5,0x49]
+# CHECK: binsli.w $w22, $w4, 0 # encoding: [0x7b,0x40,0x25,0x89]
+# CHECK: binsli.d $w6, $w2, 6 # encoding: [0x7b,0x06,0x11,0x89]
+# CHECK: binsri.b $w15, $w19, 0 # encoding: [0x7b,0xf0,0x9b,0xc9]
+# CHECK: binsri.h $w8, $w30, 1 # encoding: [0x7b,0xe1,0xf2,0x09]
+# CHECK: binsri.w $w2, $w19, 5 # encoding: [0x7b,0xc5,0x98,0x89]
+# CHECK: binsri.d $w18, $w20, 1 # encoding: [0x7b,0x81,0xa4,0x89]
+# CHECK: bnegi.b $w24, $w19, 0 # encoding: [0x7a,0xf0,0x9e,0x09]
+# CHECK: bnegi.h $w28, $w11, 3 # encoding: [0x7a,0xe3,0x5f,0x09]
+# CHECK: bnegi.w $w1, $w27, 5 # encoding: [0x7a,0xc5,0xd8,0x49]
+# CHECK: bnegi.d $w4, $w21, 1 # encoding: [0x7a,0x81,0xa9,0x09]
+# CHECK: bseti.b $w18, $w8, 0 # encoding: [0x7a,0x70,0x44,0x89]
+# CHECK: bseti.h $w24, $w14, 2 # encoding: [0x7a,0x62,0x76,0x09]
+# CHECK: bseti.w $w9, $w18, 4 # encoding: [0x7a,0x44,0x92,0x49]
+# CHECK: bseti.d $w7, $w15, 1 # encoding: [0x7a,0x01,0x79,0xc9]
+# CHECK: sat_s.b $w31, $w31, 2 # encoding: [0x78,0x72,0xff,0xca]
+# CHECK: sat_s.h $w19, $w19, 0 # encoding: [0x78,0x60,0x9c,0xca]
+# CHECK: sat_s.w $w19, $w29, 0 # encoding: [0x78,0x40,0xec,0xca]
+# CHECK: sat_s.d $w11, $w22, 0 # encoding: [0x78,0x00,0xb2,0xca]
+# CHECK: sat_u.b $w1, $w13, 3 # encoding: [0x78,0xf3,0x68,0x4a]
+# CHECK: sat_u.h $w30, $w24, 4 # encoding: [0x78,0xe4,0xc7,0x8a]
+# CHECK: sat_u.w $w31, $w13, 0 # encoding: [0x78,0xc0,0x6f,0xca]
+# CHECK: sat_u.d $w29, $w16, 5 # encoding: [0x78,0x85,0x87,0x4a]
+# CHECK: slli.b $w23, $w10, 1 # encoding: [0x78,0x71,0x55,0xc9]
+# CHECK: slli.h $w9, $w18, 1 # encoding: [0x78,0x61,0x92,0x49]
+# CHECK: slli.w $w11, $w29, 4 # encoding: [0x78,0x44,0xea,0xc9]
+# CHECK: slli.d $w25, $w20, 1 # encoding: [0x78,0x01,0xa6,0x49]
+# CHECK: srai.b $w24, $w29, 1 # encoding: [0x78,0xf1,0xee,0x09]
+# CHECK: srai.h $w1, $w6, 0 # encoding: [0x78,0xe0,0x30,0x49]
+# CHECK: srai.w $w7, $w26, 1 # encoding: [0x78,0xc1,0xd1,0xc9]
+# CHECK: srai.d $w20, $w25, 3 # encoding: [0x78,0x83,0xcd,0x09]
+# CHECK: srari.b $w5, $w25, 0 # encoding: [0x79,0x70,0xc9,0x4a]
+# CHECK: srari.h $w7, $w6, 4 # encoding: [0x79,0x64,0x31,0xca]
+# CHECK: srari.w $w17, $w11, 5 # encoding: [0x79,0x45,0x5c,0x4a]
+# CHECK: srari.d $w21, $w25, 5 # encoding: [0x79,0x05,0xcd,0x4a]
+# CHECK: srli.b $w2, $w0, 2 # encoding: [0x79,0x72,0x00,0x89]
+# CHECK: srli.h $w31, $w31, 2 # encoding: [0x79,0x62,0xff,0xc9]
+# CHECK: srli.w $w5, $w9, 4 # encoding: [0x79,0x44,0x49,0x49]
+# CHECK: srli.d $w27, $w26, 5 # encoding: [0x79,0x05,0xd6,0xc9]
+# CHECK: srlri.b $w18, $w3, 0 # encoding: [0x79,0xf0,0x1c,0x8a]
+# CHECK: srlri.h $w1, $w2, 3 # encoding: [0x79,0xe3,0x10,0x4a]
+# CHECK: srlri.w $w11, $w22, 2 # encoding: [0x79,0xc2,0xb2,0xca]
+# CHECK: srlri.d $w24, $w10, 6 # encoding: [0x79,0x86,0x56,0x0a]
+
+# CHECKOBJDUMP: bclri.b $w21, $w30, 2
+# CHECKOBJDUMP: bclri.h $w24, $w21, 0
+# CHECKOBJDUMP: bclri.w $w23, $w30, 3
+# CHECKOBJDUMP: bclri.d $w9, $w11, 0
+# CHECKOBJDUMP: binsli.b $w25, $w12, 1
+# CHECKOBJDUMP: binsli.h $w21, $w22, 0
+# CHECKOBJDUMP: binsli.w $w22, $w4, 0
+# CHECKOBJDUMP: binsli.d $w6, $w2, 6
+# CHECKOBJDUMP: binsri.b $w15, $w19, 0
+# CHECKOBJDUMP: binsri.h $w8, $w30, 1
+# CHECKOBJDUMP: binsri.w $w2, $w19, 5
+# CHECKOBJDUMP: binsri.d $w18, $w20, 1
+# CHECKOBJDUMP: bnegi.b $w24, $w19, 0
+# CHECKOBJDUMP: bnegi.h $w28, $w11, 3
+# CHECKOBJDUMP: bnegi.w $w1, $w27, 5
+# CHECKOBJDUMP: bnegi.d $w4, $w21, 1
+# CHECKOBJDUMP: bseti.b $w18, $w8, 0
+# CHECKOBJDUMP: bseti.h $w24, $w14, 2
+# CHECKOBJDUMP: bseti.w $w9, $w18, 4
+# CHECKOBJDUMP: bseti.d $w7, $w15, 1
+# CHECKOBJDUMP: sat_s.b $w31, $w31, 2
+# CHECKOBJDUMP: sat_s.h $w19, $w19, 0
+# CHECKOBJDUMP: sat_s.w $w19, $w29, 0
+# CHECKOBJDUMP: sat_s.d $w11, $w22, 0
+# CHECKOBJDUMP: sat_u.b $w1, $w13, 3
+# CHECKOBJDUMP: sat_u.h $w30, $w24, 4
+# CHECKOBJDUMP: sat_u.w $w31, $w13, 0
+# CHECKOBJDUMP: sat_u.d $w29, $w16, 5
+# CHECKOBJDUMP: slli.b $w23, $w10, 1
+# CHECKOBJDUMP: slli.h $w9, $w18, 1
+# CHECKOBJDUMP: slli.w $w11, $w29, 4
+# CHECKOBJDUMP: slli.d $w25, $w20, 1
+# CHECKOBJDUMP: srai.b $w24, $w29, 1
+# CHECKOBJDUMP: srai.h $w1, $w6, 0
+# CHECKOBJDUMP: srai.w $w7, $w26, 1
+# CHECKOBJDUMP: srai.d $w20, $w25, 3
+# CHECKOBJDUMP: srari.b $w5, $w25, 0
+# CHECKOBJDUMP: srari.h $w7, $w6, 4
+# CHECKOBJDUMP: srari.w $w17, $w11, 5
+# CHECKOBJDUMP: srari.d $w21, $w25, 5
+# CHECKOBJDUMP: srli.b $w2, $w0, 2
+# CHECKOBJDUMP: srli.h $w31, $w31, 2
+# CHECKOBJDUMP: srli.w $w5, $w9, 4
+# CHECKOBJDUMP: srli.d $w27, $w26, 5
+# CHECKOBJDUMP: srlri.b $w18, $w3, 0
+# CHECKOBJDUMP: srlri.h $w1, $w2, 3
+# CHECKOBJDUMP: srlri.w $w11, $w22, 2
+# CHECKOBJDUMP: srlri.d $w24, $w10, 6
+
+ bclri.b $w21, $w30, 2
+ bclri.h $w24, $w21, 0
+ bclri.w $w23, $w30, 3
+ bclri.d $w9, $w11, 0
+ binsli.b $w25, $w12, 1
+ binsli.h $w21, $w22, 0
+ binsli.w $w22, $w4, 0
+ binsli.d $w6, $w2, 6
+ binsri.b $w15, $w19, 0
+ binsri.h $w8, $w30, 1
+ binsri.w $w2, $w19, 5
+ binsri.d $w18, $w20, 1
+ bnegi.b $w24, $w19, 0
+ bnegi.h $w28, $w11, 3
+ bnegi.w $w1, $w27, 5
+ bnegi.d $w4, $w21, 1
+ bseti.b $w18, $w8, 0
+ bseti.h $w24, $w14, 2
+ bseti.w $w9, $w18, 4
+ bseti.d $w7, $w15, 1
+ sat_s.b $w31, $w31, 2
+ sat_s.h $w19, $w19, 0
+ sat_s.w $w19, $w29, 0
+ sat_s.d $w11, $w22, 0
+ sat_u.b $w1, $w13, 3
+ sat_u.h $w30, $w24, 4
+ sat_u.w $w31, $w13, 0
+ sat_u.d $w29, $w16, 5
+ slli.b $w23, $w10, 1
+ slli.h $w9, $w18, 1
+ slli.w $w11, $w29, 4
+ slli.d $w25, $w20, 1
+ srai.b $w24, $w29, 1
+ srai.h $w1, $w6, 0
+ srai.w $w7, $w26, 1
+ srai.d $w20, $w25, 3
+ srari.b $w5, $w25, 0
+ srari.h $w7, $w6, 4
+ srari.w $w17, $w11, 5
+ srari.d $w21, $w25, 5
+ srli.b $w2, $w0, 2
+ srli.h $w31, $w31, 2
+ srli.w $w5, $w9, 4
+ srli.d $w27, $w26, 5
+ srlri.b $w18, $w3, 0
+ srlri.h $w1, $w2, 3
+ srlri.w $w11, $w22, 2
+ srlri.d $w24, $w10, 6
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