[PATCH] Enable MISched on AArch64

[Jiangning Liu]

Tim,

I think it's a good idea to enable this new MI based scheduling at this
moment.

Apart from the problem Hao is facing right now, I think assigning value
types to virtual registers on MI is also  quite meaningful. On one hand, we
can get chance to remove redundant copy across GPR and VPR, on the other
hand we may get chance to implement flexible register allocation to improve
the code performance regarding to SISD operation.

Actually previously to help basic SISD support we did some experiments by
mapping more scalar value types to the different register classes. This way
we woulld needn't to use v1xx value type for those scalar instructions on
which we have functionality overlap between GPR class and VPR class.
Finally register allocation would be able to heuristically decide what
register class to use in terms of performance measurement.

I'm curious why you needn't to modify anything for patterns we defined in
.td files after enabling this new schduler. I expect you should have two or
three minor isuses encountered for patterns due to lack of enough value
type restrictions on those patterns we defined. Maybe this can't be exposed
until we really apply "bank selection" optimization?

Thanks,
-Jiangning
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