[llvm] r191744 - [ARM] Introduce the 'sevl' instruction in ARMv8.
Joey Gouly
joey.gouly at arm.com
Tue Oct 1 05:39:12 PDT 2013
Author: joey
Date: Tue Oct 1 07:39:11 2013
New Revision: 191744
URL: http://llvm.org/viewvc/llvm-project?rev=191744&view=rev
Log:
[ARM] Introduce the 'sevl' instruction in ARMv8.
This also removes the restriction on the immediate field of the 'hint'
instruction.
Removed:
llvm/trunk/test/MC/ARM/invalid-hint-arm.s
llvm/trunk/test/MC/ARM/invalid-hint-thumb.s
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsARM.td
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
llvm/trunk/test/CodeGen/ARM/intrinsics-v8.ll
llvm/trunk/test/MC/ARM/basic-arm-instructions-v8.s
llvm/trunk/test/MC/ARM/basic-arm-instructions.s
llvm/trunk/test/MC/ARM/basic-thumb2-instructions-v8.s
llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt
llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt
Modified: llvm/trunk/include/llvm/IR/IntrinsicsARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsARM.td?rev=191744&r1=191743&r2=191744&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsARM.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsARM.td Tue Oct 1 07:39:11 2013
@@ -113,6 +113,10 @@ def int_arm_crc32cw : Intrinsic<[llvm_i3
[IntrNoMem]>;
//===----------------------------------------------------------------------===//
+// HINT
+def int_arm_sevl : Intrinsic<[], []>;
+
+//===----------------------------------------------------------------------===//
// Advanced SIMD (NEON)
// The following classes do not correspond directly to GCC builtins.
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=191744&r1=191743&r2=191744&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Oct 1 07:39:11 2013
@@ -594,17 +594,6 @@ def imm0_1 : Operand<i32> { let ParserMa
def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
-/// imm0_4 predicate - Immediate in the range [0,4].
-def Imm0_4AsmOperand : ImmAsmOperand
-{
- let Name = "Imm0_4";
- let DiagnosticType = "ImmRange0_4";
-}
-def imm0_4 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 5; }]> {
- let ParserMatchClass = Imm0_4AsmOperand;
- let DecoderMethod = "DecodeImm0_4";
-}
-
/// imm0_7 predicate - Immediate in the range [0,7].
def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
@@ -1677,11 +1666,11 @@ PseudoInst<(outs), (ins i32imm:$amt, pre
[(ARMcallseq_start timm:$amt)]>;
}
-def HINT : AI<(outs), (ins imm0_4:$imm), MiscFrm, NoItinerary,
+def HINT : AI<(outs), (ins imm0_255:$imm), MiscFrm, NoItinerary,
"hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
- bits<3> imm;
- let Inst{27-3} = 0b0011001000001111000000000;
- let Inst{2-0} = imm;
+ bits<8> imm;
+ let Inst{27-8} = 0b00110010000011110000;
+ let Inst{7-0} = imm;
}
def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
@@ -1689,6 +1678,9 @@ def : InstAlias<"yield$p", (HINT 1, pred
def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
+def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
+
+def : Pat<(int_arm_sevl), (HINT 5)>;
def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
"\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=191744&r1=191743&r2=191744&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Oct 1 07:39:11 2013
@@ -289,6 +289,11 @@ def tSEV : T1pI<(outs), (ins), NoItinera
T1SystemEncoding<0x40>, // A8.6.157
Requires<[IsThumb2]>;
+def tSEVL : T1pI<(outs), (ins), NoItinerary, "sevl", "", [(int_arm_sevl)]>,
+ T1SystemEncoding<0x50>,
+ Requires<[IsThumb2, HasV8]>;
+
+
// The imm operand $val can be used by a debugger to store more information
// about the breakpoint.
def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=191744&r1=191743&r2=191744&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Oct 1 07:39:11 2013
@@ -3652,18 +3652,21 @@ def : t2InstAlias<"cps.w $mode", (t2CPS1
// A6.3.4 Branches and miscellaneous control
// Table A6-14 Change Processor State, and hint instructions
-def t2HINT : T2I<(outs), (ins imm0_4:$imm), NoItinerary, "hint", "\t$imm",[]> {
+def t2HINT : T2I<(outs), (ins imm0_255:$imm), NoItinerary, "hint", "\t$imm",[]> {
bits<3> imm;
let Inst{31-3} = 0b11110011101011111000000000000;
let Inst{2-0} = imm;
}
-def : t2InstAlias<"hint$p.w $imm", (t2HINT imm0_4:$imm, pred:$p)>;
+def : t2InstAlias<"hint$p.w $imm", (t2HINT imm0_255:$imm, pred:$p)>;
def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p)>;
def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p)>;
def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p)>;
def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p)>;
def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p)>;
+def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p)> {
+ let Predicates = [IsThumb2, HasV8];
+}
def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
bits<4> opt;
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=191744&r1=191743&r2=191744&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Oct 1 07:39:11 2013
@@ -679,13 +679,6 @@ public:
int64_t Value = CE->getValue();
return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
}
- bool isImm0_4() const {
- if (!isImm()) return false;
- const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- if (!CE) return false;
- int64_t Value = CE->getValue();
- return Value >= 0 && Value < 5;
- }
bool isImm0_1020s4() const {
if (!isImm()) return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
@@ -7687,11 +7680,6 @@ MatchAndEmitInstruction(SMLoc IDLoc, uns
return Error(IDLoc, "instruction variant requires ARMv6 or later");
case Match_RequiresThumb2:
return Error(IDLoc, "instruction variant requires Thumb2");
- case Match_ImmRange0_4: {
- SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
- if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
- return Error(ErrorLoc, "immediate operand must be in the range [0,4]");
- }
case Match_ImmRange0_15: {
SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=191744&r1=191743&r2=191744&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Oct 1 07:39:11 2013
@@ -84,6 +84,11 @@ void ARMInstPrinter::printInst(const MCI
case 2: O << "\twfe"; break;
case 3: O << "\twfi"; break;
case 4: O << "\tsev"; break;
+ case 5:
+ if ((getAvailableFeatures() & ARM::HasV8Ops)) {
+ O << "\tsevl";
+ break;
+ } // Fallthrough for non-v8
default:
// Anything else should just print normally.
printInstruction(MI, O);
Modified: llvm/trunk/test/CodeGen/ARM/intrinsics-v8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/intrinsics-v8.ll?rev=191744&r1=191743&r2=191744&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/intrinsics-v8.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/intrinsics-v8.ll Tue Oct 1 07:39:11 2013
@@ -9,8 +9,11 @@ define void @test() {
call void @llvm.arm.dsb(i32 15)
; CHECK: dsb ishld
call void @llvm.arm.dsb(i32 9)
+ ; CHECK: sevl
+ tail call void @llvm.arm.sevl() nounwind
ret void
}
declare void @llvm.arm.dmb(i32)
declare void @llvm.arm.dsb(i32)
+declare void @llvm.arm.sevl() nounwind
Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions-v8.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions-v8.s?rev=191744&r1=191743&r2=191744&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions-v8.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions-v8.s Tue Oct 1 07:39:11 2013
@@ -50,3 +50,10 @@
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
+
+ at ------------------------------------------------------------------------------
+@ SEVL
+ at ------------------------------------------------------------------------------
+ sevl
+
+@ CHECK: sevl @ encoding: [0x05,0xf0,0x20,0xe3]
Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=191744&r1=191743&r2=191744&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Tue Oct 1 07:39:11 2013
@@ -2928,6 +2928,7 @@ Lforward:
hint #2
hint #1
hint #0
+ hint #255
@ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3]
@ CHECK: wfehi @ encoding: [0x02,0xf0,0x20,0x83]
@@ -2940,3 +2941,4 @@ Lforward:
@ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3]
@ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3]
@ CHECK: nop @ encoding: [0x00,0xf0,0x20,0xe3]
+@ CHECK: hint #255 @ encoding: [0xff,0xf0,0x20,0xe3]
Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions-v8.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions-v8.s?rev=191744&r1=191743&r2=191744&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions-v8.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions-v8.s Tue Oct 1 07:39:11 2013
@@ -69,3 +69,16 @@
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
+
+ at ------------------------------------------------------------------------------
+@ SEVL
+ at ------------------------------------------------------------------------------
+ sevl
+ sevl.w
+ it ge
+ sevlge
+
+@ CHECK-V8: sevl @ encoding: [0x50,0xbf]
+@ CHECK-V8: sevl.w @ encoding: [0xaf,0xf3,0x05,0x80]
+@ CHECK-V8: it ge @ encoding: [0xa8,0xbf]
+@ CHECK-V8: sevlge @ encoding: [0x50,0xbf]
Removed: llvm/trunk/test/MC/ARM/invalid-hint-arm.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/invalid-hint-arm.s?rev=191743&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/invalid-hint-arm.s (original)
+++ llvm/trunk/test/MC/ARM/invalid-hint-arm.s (removed)
@@ -1,7 +0,0 @@
-@ RUN: not llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 < %s 2>&1 | FileCheck %s
-
-hint #5
-hint #100
-
-@ CHECK: error: immediate operand must be in the range [0,4]
-@ CHECK: error: immediate operand must be in the range [0,4]
Removed: llvm/trunk/test/MC/ARM/invalid-hint-thumb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/invalid-hint-thumb.s?rev=191743&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/invalid-hint-thumb.s (original)
+++ llvm/trunk/test/MC/ARM/invalid-hint-thumb.s (removed)
@@ -1,9 +0,0 @@
-@ RUN: not llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 < %s 2>&1 | FileCheck %s
-
-hint #5
-hint.w #5
-hint #100
-
-@ CHECK: error: immediate operand must be in the range [0,4]
-@ CHECK: error: immediate operand must be in the range [0,4]
-@ CHECK: error: immediate operand must be in the range [0,4]
Modified: llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt?rev=191744&r1=191743&r2=191744&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt Tue Oct 1 07:39:11 2013
@@ -18,3 +18,6 @@
# CHECK: dmb oshld
# CHECK: dmb nshld
# CHECK: dmb ld
+
+0x05 0xf0 0x20 0xe3
+# CHECK: sevl
Modified: llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt?rev=191744&r1=191743&r2=191744&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt Tue Oct 1 07:39:11 2013
@@ -2420,6 +2420,7 @@
# CHECK: wfilt
# CHECK: yield
# CHECK: yieldne
+# CHECK: hint #5
0x02 0xf0 0x20 0xe3
0x02 0xf0 0x20 0x83
@@ -2427,3 +2428,4 @@
0x03 0xf0 0x20 0xb3
0x01 0xf0 0x20 0xe3
0x01 0xf0 0x20 0x13
+0x05 0xf0 0x20 0xe3
Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt?rev=191744&r1=191743&r2=191744&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt Tue Oct 1 07:39:11 2013
@@ -69,14 +69,6 @@
# Undefined encoding space for hint instructions
#------------------------------------------------------------------------------
-[0x05 0xf0 0x20 0xe3]
-# CHECK: invalid instruction encoding
-# CHECK-NEXT: [0x05 0xf0 0x20 0xe3]
-
-[0x41 0xf0 0x20 0xe3]
-# CHECK: invalid instruction encoding
-# CHECK-NEXT: [0x41 0xf0 0x20 0xe3]
-
# FIXME: is it "dbg #14" or not????
[0xfe 0xf0 0x20 0xe3]
# CHCK: invalid instruction encoding
Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt?rev=191744&r1=191743&r2=191744&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt Tue Oct 1 07:39:11 2013
@@ -37,10 +37,9 @@
# Undefined encoding space for hint instructions
#------------------------------------------------------------------------------
-[0xaf 0xf3 0x05 0x80]
+[0x60 0xbf]
# CHECK: invalid instruction encoding
-# CHECK-NEXT: [0xaf 0xf3 0x05 0x80]
-
+# CHECK-NEXT: [0x60 0xbf]
#------------------------------------------------------------------------------
# Undefined encoding for it
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