[llvm] r191687 - [mips][msa] Direct Object Emission for I5 instructions.
Jack Carter
jack.carter at imgtec.com
Mon Sep 30 10:58:08 PDT 2013
Author: jacksprat
Date: Mon Sep 30 12:58:07 2013
New Revision: 191687
URL: http://llvm.org/viewvc/llvm-project?rev=191687&view=rev
Log:
[mips][msa] Direct Object Emission for I5 instructions.
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.
Patch by Matheus Almeida
Added:
llvm/trunk/test/MC/Mips/msa/test_i5.s
Modified:
llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td?rev=191687&r1=191686&r2=191687&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td Mon Sep 30 12:58:07 2013
@@ -134,8 +134,15 @@ class MSA_ELM_D_FMT<bits<4> major, bits<
}
class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
+ bits<5> imm;
+ bits<5> ws;
+ bits<5> wd;
+
let Inst{25-23} = major;
let Inst{22-21} = df;
+ let Inst{20-16} = imm;
+ let Inst{15-11} = ws;
+ let Inst{10-6} = wd;
let Inst{5-0} = minor;
}
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td?rev=191687&r1=191686&r2=191687&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td Mon Sep 30 12:58:07 2013
@@ -1084,13 +1084,13 @@ class MSA_COPY_PSEUDO_BASE<SDPatternOper
}
class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- SplatComplexPattern SplatImm, RegisterClass RCWD,
- RegisterClass RCWS = RCWD,
+ SplatComplexPattern SplatImm, RegisterOperand ROWD,
+ RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
- dag OutOperandList = (outs RCWD:$wd);
- dag InOperandList = (ins RCWS:$ws, SplatImm.OpClass:$imm);
+ dag OutOperandList = (outs ROWD:$wd);
+ dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
- list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, SplatImm:$imm))];
+ list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
InstrItinClass Itinerary = itin;
}
@@ -1334,10 +1334,14 @@ class ADDV_H_DESC : MSA_3R_DESC_BASE<"ad
class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
-class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5, MSA128B>;
-class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5, MSA128H>;
-class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5, MSA128W>;
-class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5, MSA128D>;
+class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
+ MSA128BOpnd>;
+class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
+ MSA128HOpnd>;
+class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
+ MSA128WOpnd>;
+class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
+ MSA128DOpnd>;
class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128B>;
class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128H>;
@@ -1511,13 +1515,13 @@ class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq
IsCommutable;
class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
- MSA128B>;
+ MSA128BOpnd>;
class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
- MSA128H>;
+ MSA128HOpnd>;
class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
- MSA128W>;
+ MSA128WOpnd>;
class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
- MSA128D>;
+ MSA128DOpnd>;
class CFCMSA_DESC {
dag OutOperandList = (outs GPR32:$rd);
@@ -1538,22 +1542,22 @@ class CLE_U_W_DESC : MSA_3R_DESC_BASE<"c
class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
- vsplati8_simm5, MSA128B>;
+ vsplati8_simm5, MSA128BOpnd>;
class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
- vsplati16_simm5, MSA128H>;
+ vsplati16_simm5, MSA128HOpnd>;
class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
- vsplati32_simm5, MSA128W>;
+ vsplati32_simm5, MSA128WOpnd>;
class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
- vsplati64_simm5, MSA128D>;
+ vsplati64_simm5, MSA128DOpnd>;
class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
- vsplati8_uimm5, MSA128B>;
+ vsplati8_uimm5, MSA128BOpnd>;
class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
- vsplati16_uimm5, MSA128H>;
+ vsplati16_uimm5, MSA128HOpnd>;
class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
- vsplati32_uimm5, MSA128W>;
+ vsplati32_uimm5, MSA128WOpnd>;
class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
- vsplati64_uimm5, MSA128D>;
+ vsplati64_uimm5, MSA128DOpnd>;
class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
@@ -1566,22 +1570,22 @@ class CLT_U_W_DESC : MSA_3R_DESC_BASE<"c
class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
- vsplati8_simm5, MSA128B>;
+ vsplati8_simm5, MSA128BOpnd>;
class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
- vsplati16_simm5, MSA128H>;
+ vsplati16_simm5, MSA128HOpnd>;
class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
- vsplati32_simm5, MSA128W>;
+ vsplati32_simm5, MSA128WOpnd>;
class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
- vsplati64_simm5, MSA128D>;
+ vsplati64_simm5, MSA128DOpnd>;
class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
- vsplati8_uimm5, MSA128B>;
+ vsplati8_uimm5, MSA128BOpnd>;
class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
- vsplati16_uimm5, MSA128H>;
+ vsplati16_uimm5, MSA128HOpnd>;
class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
- vsplati32_uimm5, MSA128W>;
+ vsplati32_uimm5, MSA128WOpnd>;
class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
- vsplati64_uimm5, MSA128D>;
+ vsplati64_uimm5, MSA128DOpnd>;
class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8,
GPR32, MSA128B>;
@@ -2045,22 +2049,22 @@ class MAX_U_W_DESC : MSA_3R_DESC_BASE<"m
class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>;
class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5,
- MSA128B>;
+ MSA128BOpnd>;
class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5,
- MSA128H>;
+ MSA128HOpnd>;
class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5,
- MSA128W>;
+ MSA128WOpnd>;
class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5,
- MSA128D>;
+ MSA128DOpnd>;
class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5,
- MSA128B>;
+ MSA128BOpnd>;
class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5,
- MSA128H>;
+ MSA128HOpnd>;
class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5,
- MSA128W>;
+ MSA128WOpnd>;
class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5,
- MSA128D>;
+ MSA128DOpnd>;
class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
@@ -2078,22 +2082,22 @@ class MIN_U_W_DESC : MSA_3R_DESC_BASE<"m
class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>;
class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5,
- MSA128B>;
+ MSA128BOpnd>;
class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5,
- MSA128H>;
+ MSA128HOpnd>;
class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5,
- MSA128W>;
+ MSA128WOpnd>;
class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5,
- MSA128D>;
+ MSA128DOpnd>;
class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5,
- MSA128B>;
+ MSA128BOpnd>;
class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5,
- MSA128H>;
+ MSA128HOpnd>;
class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5,
- MSA128W>;
+ MSA128WOpnd>;
class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5,
- MSA128D>;
+ MSA128DOpnd>;
class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", int_mips_mod_s_b, MSA128BOpnd>;
class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", int_mips_mod_s_h, MSA128HOpnd>;
@@ -2364,10 +2368,14 @@ class SUBV_H_DESC : MSA_3R_DESC_BASE<"su
class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
-class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5, MSA128B>;
-class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5, MSA128H>;
-class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5, MSA128W>;
-class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5, MSA128D>;
+class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
+ MSA128BOpnd>;
+class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
+ MSA128HOpnd>;
+class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
+ MSA128WOpnd>;
+class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
+ MSA128DOpnd>;
class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
Added: llvm/trunk/test/MC/Mips/msa/test_i5.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/msa/test_i5.s?rev=191687&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/msa/test_i5.s (added)
+++ llvm/trunk/test/MC/Mips/msa/test_i5.s Mon Sep 30 12:58:07 2013
@@ -0,0 +1,138 @@
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 -mattr=+msa -arch=mips | FileCheck %s
+#
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+msa -arch=mips -filetype=obj -o - | llvm-objdump -d -triple=mipsel-unknown-linux -mattr=+msa -arch=mips - | FileCheck %s -check-prefix=CHECKOBJDUMP
+#
+# CHECK: addvi.b $w3, $w31, 30 # encoding: [0x78,0x1e,0xf8,0xc6]
+# CHECK: addvi.h $w24, $w13, 26 # encoding: [0x78,0x3a,0x6e,0x06]
+# CHECK: addvi.w $w26, $w20, 26 # encoding: [0x78,0x5a,0xa6,0x86]
+# CHECK: addvi.d $w16, $w1, 21 # encoding: [0x78,0x75,0x0c,0x06]
+# CHECK: ceqi.b $w24, $w21, -8 # encoding: [0x78,0x18,0xae,0x07]
+# CHECK: ceqi.h $w31, $w15, 2 # encoding: [0x78,0x22,0x7f,0xc7]
+# CHECK: ceqi.w $w12, $w1, -1 # encoding: [0x78,0x5f,0x0b,0x07]
+# CHECK: ceqi.d $w24, $w22, 7 # encoding: [0x78,0x67,0xb6,0x07]
+# CHECK: clei_s.b $w12, $w16, 1 # encoding: [0x7a,0x01,0x83,0x07]
+# CHECK: clei_s.h $w2, $w10, -9 # encoding: [0x7a,0x37,0x50,0x87]
+# CHECK: clei_s.w $w4, $w11, -10 # encoding: [0x7a,0x56,0x59,0x07]
+# CHECK: clei_s.d $w0, $w29, -10 # encoding: [0x7a,0x76,0xe8,0x07]
+# CHECK: clei_u.b $w21, $w17, 3 # encoding: [0x7a,0x83,0x8d,0x47]
+# CHECK: clei_u.h $w29, $w7, 17 # encoding: [0x7a,0xb1,0x3f,0x47]
+# CHECK: clei_u.w $w1, $w1, 2 # encoding: [0x7a,0xc2,0x08,0x47]
+# CHECK: clei_u.d $w27, $w27, 29 # encoding: [0x7a,0xfd,0xde,0xc7]
+# CHECK: clti_s.b $w19, $w13, -7 # encoding: [0x79,0x19,0x6c,0xc7]
+# CHECK: clti_s.h $w15, $w10, -12 # encoding: [0x79,0x34,0x53,0xc7]
+# CHECK: clti_s.w $w12, $w12, 11 # encoding: [0x79,0x4b,0x63,0x07]
+# CHECK: clti_s.d $w29, $w20, -15 # encoding: [0x79,0x71,0xa7,0x47]
+# CHECK: clti_u.b $w14, $w9, 29 # encoding: [0x79,0x9d,0x4b,0x87]
+# CHECK: clti_u.h $w24, $w25, 25 # encoding: [0x79,0xb9,0xce,0x07]
+# CHECK: clti_u.w $w1, $w1, 22 # encoding: [0x79,0xd6,0x08,0x47]
+# CHECK: clti_u.d $w21, $w25, 1 # encoding: [0x79,0xe1,0xcd,0x47]
+# CHECK: maxi_s.b $w22, $w21, 1 # encoding: [0x79,0x01,0xad,0x86]
+# CHECK: maxi_s.h $w29, $w5, -8 # encoding: [0x79,0x38,0x2f,0x46]
+# CHECK: maxi_s.w $w1, $w10, -12 # encoding: [0x79,0x54,0x50,0x46]
+# CHECK: maxi_s.d $w13, $w29, -16 # encoding: [0x79,0x70,0xeb,0x46]
+# CHECK: maxi_u.b $w20, $w0, 12 # encoding: [0x79,0x8c,0x05,0x06]
+# CHECK: maxi_u.h $w1, $w14, 3 # encoding: [0x79,0xa3,0x70,0x46]
+# CHECK: maxi_u.w $w27, $w22, 11 # encoding: [0x79,0xcb,0xb6,0xc6]
+# CHECK: maxi_u.d $w26, $w6, 4 # encoding: [0x79,0xe4,0x36,0x86]
+# CHECK: mini_s.b $w4, $w1, 1 # encoding: [0x7a,0x01,0x09,0x06]
+# CHECK: mini_s.h $w27, $w27, -9 # encoding: [0x7a,0x37,0xde,0xc6]
+# CHECK: mini_s.w $w28, $w11, 9 # encoding: [0x7a,0x49,0x5f,0x06]
+# CHECK: mini_s.d $w11, $w10, 10 # encoding: [0x7a,0x6a,0x52,0xc6]
+# CHECK: mini_u.b $w18, $w23, 27 # encoding: [0x7a,0x9b,0xbc,0x86]
+# CHECK: mini_u.h $w7, $w26, 18 # encoding: [0x7a,0xb2,0xd1,0xc6]
+# CHECK: mini_u.w $w11, $w12, 26 # encoding: [0x7a,0xda,0x62,0xc6]
+# CHECK: mini_u.d $w11, $w15, 2 # encoding: [0x7a,0xe2,0x7a,0xc6]
+# CHECK: subvi.b $w24, $w20, 19 # encoding: [0x78,0x93,0xa6,0x06]
+# CHECK: subvi.h $w11, $w19, 4 # encoding: [0x78,0xa4,0x9a,0xc6]
+# CHECK: subvi.w $w12, $w10, 11 # encoding: [0x78,0xcb,0x53,0x06]
+# CHECK: subvi.d $w19, $w16, 7 # encoding: [0x78,0xe7,0x84,0xc6]
+
+# CHECKOBJDUMP: addvi.b $w3, $w31, 30
+# CHECKOBJDUMP: addvi.h $w24, $w13, 26
+# CHECKOBJDUMP: addvi.w $w26, $w20, 26
+# CHECKOBJDUMP: addvi.d $w16, $w1, 21
+# CHECKOBJDUMP: ceqi.b $w24, $w21, 24
+# CHECKOBJDUMP: ceqi.h $w31, $w15, 2
+# CHECKOBJDUMP: ceqi.w $w12, $w1, 31
+# CHECKOBJDUMP: ceqi.d $w24, $w22, 7
+# CHECKOBJDUMP: clei_s.b $w12, $w16, 1
+# CHECKOBJDUMP: clei_s.h $w2, $w10, 23
+# CHECKOBJDUMP: clei_s.w $w4, $w11, 22
+# CHECKOBJDUMP: clei_s.d $w0, $w29, 22
+# CHECKOBJDUMP: clei_u.b $w21, $w17, 3
+# CHECKOBJDUMP: clei_u.h $w29, $w7, 17
+# CHECKOBJDUMP: clei_u.w $w1, $w1, 2
+# CHECKOBJDUMP: clei_u.d $w27, $w27, 29
+# CHECKOBJDUMP: clti_s.b $w19, $w13, 25
+# CHECKOBJDUMP: clti_s.h $w15, $w10, 20
+# CHECKOBJDUMP: clti_s.w $w12, $w12, 11
+# CHECKOBJDUMP: clti_s.d $w29, $w20, 17
+# CHECKOBJDUMP: clti_u.b $w14, $w9, 29
+# CHECKOBJDUMP: clti_u.h $w24, $w25, 25
+# CHECKOBJDUMP: clti_u.w $w1, $w1, 22
+# CHECKOBJDUMP: clti_u.d $w21, $w25, 1
+# CHECKOBJDUMP: maxi_s.b $w22, $w21, 1
+# CHECKOBJDUMP: maxi_s.h $w29, $w5, 24
+# CHECKOBJDUMP: maxi_s.w $w1, $w10, 20
+# CHECKOBJDUMP: maxi_s.d $w13, $w29, 16
+# CHECKOBJDUMP: maxi_u.b $w20, $w0, 12
+# CHECKOBJDUMP: maxi_u.h $w1, $w14, 3
+# CHECKOBJDUMP: maxi_u.w $w27, $w22, 11
+# CHECKOBJDUMP: maxi_u.d $w26, $w6, 4
+# CHECKOBJDUMP: mini_s.b $w4, $w1, 1
+# CHECKOBJDUMP: mini_s.h $w27, $w27, 23
+# CHECKOBJDUMP: mini_s.w $w28, $w11, 9
+# CHECKOBJDUMP: mini_s.d $w11, $w10, 10
+# CHECKOBJDUMP: mini_u.b $w18, $w23, 27
+# CHECKOBJDUMP: mini_u.h $w7, $w26, 18
+# CHECKOBJDUMP: mini_u.w $w11, $w12, 26
+# CHECKOBJDUMP: mini_u.d $w11, $w15, 2
+# CHECKOBJDUMP: subvi.b $w24, $w20, 19
+# CHECKOBJDUMP: subvi.h $w11, $w19, 4
+# CHECKOBJDUMP: subvi.w $w12, $w10, 11
+# CHECKOBJDUMP: subvi.d $w19, $w16, 7
+
+ addvi.b $w3, $w31, 30
+ addvi.h $w24, $w13, 26
+ addvi.w $w26, $w20, 26
+ addvi.d $w16, $w1, 21
+ ceqi.b $w24, $w21, -8
+ ceqi.h $w31, $w15, 2
+ ceqi.w $w12, $w1, -1
+ ceqi.d $w24, $w22, 7
+ clei_s.b $w12, $w16, 1
+ clei_s.h $w2, $w10, -9
+ clei_s.w $w4, $w11, -10
+ clei_s.d $w0, $w29, -10
+ clei_u.b $w21, $w17, 3
+ clei_u.h $w29, $w7, 17
+ clei_u.w $w1, $w1, 2
+ clei_u.d $w27, $w27, 29
+ clti_s.b $w19, $w13, -7
+ clti_s.h $w15, $w10, -12
+ clti_s.w $w12, $w12, 11
+ clti_s.d $w29, $w20, -15
+ clti_u.b $w14, $w9, 29
+ clti_u.h $w24, $w25, 25
+ clti_u.w $w1, $w1, 22
+ clti_u.d $w21, $w25, 1
+ maxi_s.b $w22, $w21, 1
+ maxi_s.h $w29, $w5, -8
+ maxi_s.w $w1, $w10, -12
+ maxi_s.d $w13, $w29, -16
+ maxi_u.b $w20, $w0, 12
+ maxi_u.h $w1, $w14, 3
+ maxi_u.w $w27, $w22, 11
+ maxi_u.d $w26, $w6, 4
+ mini_s.b $w4, $w1, 1
+ mini_s.h $w27, $w27, -9
+ mini_s.w $w28, $w11, 9
+ mini_s.d $w11, $w10, 10
+ mini_u.b $w18, $w23, 27
+ mini_u.h $w7, $w26, 18
+ mini_u.w $w11, $w12, 26
+ mini_u.d $w11, $w15, 2
+ subvi.b $w24, $w20, 19
+ subvi.h $w11, $w19, 4
+ subvi.w $w12, $w10, 11
+ subvi.d $w19, $w16, 7
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