[llvm] r191337 - Add missing check to SETCC optimization.

Eli Friedman eli.friedman at gmail.com
Tue Sep 24 15:50:14 PDT 2013


Author: efriedma
Date: Tue Sep 24 17:50:14 2013
New Revision: 191337

URL: http://llvm.org/viewvc/llvm-project?rev=191337&view=rev
Log:
Add missing check to SETCC optimization.

PR17338.

Added:
    llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=191337&r1=191336&r2=191337&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Sep 24 17:50:14 2013
@@ -1185,6 +1185,7 @@ TargetLowering::SimplifySetCC(EVT VT, SD
     // the test is for equality or unsigned, and all 1 bits of the const are
     // in the same partial word, see if we can shorten the load.
     if (DCI.isBeforeLegalize() &&
+        !ISD::isSignedIntSetCC(Cond) &&
         N0.getOpcode() == ISD::AND && C1 == 0 &&
         N0.getNode()->hasOneUse() &&
         isa<LoadSDNode>(N0.getOperand(0)) &&

Added: llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll?rev=191337&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll (added)
+++ llvm/trunk/test/CodeGen/X86/setcc-narrowing.ll Tue Sep 24 17:50:14 2013
@@ -0,0 +1,18 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin | FileCheck %s
+; PR17338
+
+ at t1.global = internal global i64 -1, align 8
+
+define i32 @t1() nounwind ssp {
+entry:
+; CHECK-LABEL: t1:
+; CHECK: cmpl	$0, _t1.global
+; CHECK-NEXT: setne %al
+; CHECK-NEXT: movzbl %al, %eax
+; CHECK-NEXT: ret
+  %0 = load i64* @t1.global, align 8
+  %and = and i64 4294967295, %0
+  %cmp = icmp sgt i64 %and, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}





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