[llvm] r191293 - [mips][msa] Added support for matching andi, ori, nori, and xori from normal IR (i.e. not intrinsics)
Daniel Sanders
daniel.sanders at imgtec.com
Tue Sep 24 05:32:47 PDT 2013
Author: dsanders
Date: Tue Sep 24 07:32:47 2013
New Revision: 191293
URL: http://llvm.org/viewvc/llvm-project?rev=191293&view=rev
Log:
[mips][msa] Added support for matching andi, ori, nori, and xori from normal IR (i.e. not intrinsics)
Modified:
llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td?rev=191293&r1=191292&r2=191293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td Tue Sep 24 07:32:47 2013
@@ -991,11 +991,24 @@ class MSA_SI5_DESC_BASE<string instr_asm
}
class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- RegisterClass RCWD, RegisterClass RCWS = RCWD,
+ SDPatternOperator SplatNode, RegisterClass RCWD,
+ RegisterClass RCWS = RCWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs RCWD:$wd);
dag InOperandList = (ins RCWS:$ws, uimm8:$u8);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
+ list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws,
+ (SplatNode immZExt8:$u8)))];
+ InstrItinClass Itinerary = itin;
+}
+
+// This class is deprecated and will be removed in the next few patches
+class MSA_I8_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
+ RegisterClass RCWD, RegisterClass RCWS = RCWD,
+ InstrItinClass itin = NoItinerary> {
+ dag OutOperandList = (outs RCWD:$wd);
+ dag InOperandList = (ins RCWS:$ws, uimm8:$u8);
+ string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, immZExt8:$u8))];
InstrItinClass Itinerary = itin;
}
@@ -1168,7 +1181,7 @@ class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEU
class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128W>;
class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128D>;
-class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", int_mips_andi_b, MSA128B>;
+class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8, MSA128B>;
class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b, MSA128B>;
class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h, MSA128H>;
@@ -1256,11 +1269,11 @@ class BINSRI_D_DESC : MSA_BIT_D_DESC_BAS
class BMNZ_V_DESC : MSA_VEC_DESC_BASE<"bmnz.v", int_mips_bmnz_v, MSA128B>;
-class BMNZI_B_DESC : MSA_I8_DESC_BASE<"bmnzi.b", int_mips_bmnzi_b, MSA128B>;
+class BMNZI_B_DESC : MSA_I8_X_DESC_BASE<"bmnzi.b", int_mips_bmnzi_b, MSA128B>;
class BMZ_V_DESC : MSA_VEC_DESC_BASE<"bmz.v", int_mips_bmz_v, MSA128B>;
-class BMZI_B_DESC : MSA_I8_DESC_BASE<"bmzi.b", int_mips_bmzi_b, MSA128B>;
+class BMZI_B_DESC : MSA_I8_X_DESC_BASE<"bmzi.b", int_mips_bmzi_b, MSA128B>;
class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", int_mips_bneg_b, MSA128B>;
class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", int_mips_bneg_h, MSA128H>;
@@ -1929,14 +1942,14 @@ class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEU
class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128W>;
class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128D>;
-class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", int_mips_nori_b, MSA128B>;
+class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8, MSA128B>;
class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128B>;
class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128H>;
class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128W>;
class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128D>;
-class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", int_mips_ori_b, MSA128B>;
+class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8, MSA128B>;
class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", int_mips_pckev_b, MSA128B>;
class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", int_mips_pckev_h, MSA128H>;
@@ -1963,9 +1976,9 @@ class SAT_U_H_DESC : MSA_BIT_H_DESC_BASE
class SAT_U_W_DESC : MSA_BIT_W_DESC_BASE<"sat_u.w", int_mips_sat_u_w, MSA128W>;
class SAT_U_D_DESC : MSA_BIT_D_DESC_BASE<"sat_u.d", int_mips_sat_u_d, MSA128D>;
-class SHF_B_DESC : MSA_I8_DESC_BASE<"shf.b", int_mips_shf_b, MSA128B>;
-class SHF_H_DESC : MSA_I8_DESC_BASE<"shf.h", int_mips_shf_h, MSA128H>;
-class SHF_W_DESC : MSA_I8_DESC_BASE<"shf.w", int_mips_shf_w, MSA128W>;
+class SHF_B_DESC : MSA_I8_X_DESC_BASE<"shf.b", int_mips_shf_b, MSA128B>;
+class SHF_H_DESC : MSA_I8_X_DESC_BASE<"shf.h", int_mips_shf_h, MSA128H>;
+class SHF_W_DESC : MSA_I8_X_DESC_BASE<"shf.w", int_mips_shf_w, MSA128W>;
class SLD_B_DESC : MSA_3R_DESC_BASE<"sld.b", int_mips_sld_b, MSA128B>;
class SLD_H_DESC : MSA_3R_DESC_BASE<"sld.h", int_mips_sld_h, MSA128H>;
@@ -2125,7 +2138,7 @@ class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEU
class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128W>;
class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128D>;
-class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", int_mips_xori_b, MSA128B>;
+class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8, MSA128B>;
// Instruction defs.
def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=191293&r1=191292&r2=191293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp Tue Sep 24 07:32:47 2013
@@ -1153,6 +1153,9 @@ SDValue MipsSETargetLowering::lowerINTRI
lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_and_v:
return lowerMSABinaryIntr(Op, DAG, ISD::AND);
+ case Intrinsic::mips_andi_b:
+ return lowerMSABinaryImmIntr(Op, DAG, ISD::AND,
+ lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_bnz_b:
case Intrinsic::mips_bnz_h:
case Intrinsic::mips_bnz_w:
@@ -1386,8 +1389,16 @@ SDValue MipsSETargetLowering::lowerINTRI
SDValue Res = lowerMSABinaryIntr(Op, DAG, ISD::OR);
return DAG.getNOT(SDLoc(Op), Res, Res->getValueType(0));
}
+ case Intrinsic::mips_nori_b: {
+ SDValue Res = lowerMSABinaryImmIntr(Op, DAG, ISD::OR,
+ lowerMSASplatImm(Op, 2, DAG));
+ return DAG.getNOT(SDLoc(Op), Res, Res->getValueType(0));
+ }
case Intrinsic::mips_or_v:
return lowerMSABinaryIntr(Op, DAG, ISD::OR);
+ case Intrinsic::mips_ori_b:
+ return lowerMSABinaryImmIntr(Op, DAG, ISD::OR,
+ lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_pcnt_b:
case Intrinsic::mips_pcnt_h:
case Intrinsic::mips_pcnt_w:
@@ -1439,6 +1450,9 @@ SDValue MipsSETargetLowering::lowerINTRI
lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_xor_v:
return lowerMSABinaryIntr(Op, DAG, ISD::XOR);
+ case Intrinsic::mips_xori_b:
+ return lowerMSABinaryImmIntr(Op, DAG, ISD::XOR,
+ lowerMSASplatImm(Op, 2, DAG));
}
}
Modified: llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll?rev=191293&r1=191292&r2=191293&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll Tue Sep 24 07:32:47 2013
@@ -64,6 +64,65 @@ define void @and_v2i64(<2 x i64>* %c, <2
; CHECK: .size and_v2i64
}
+define void @and_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
+ ; CHECK: and_v16i8_i:
+
+ %1 = load <16 x i8>* %a
+ ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
+ %2 = and <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ ; CHECK-DAG: andi.b [[R4:\$w[0-9]+]], [[R1]], 1
+ store <16 x i8> %2, <16 x i8>* %c
+ ; CHECK-DAG: st.b [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size and_v16i8_i
+}
+
+define void @and_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
+ ; CHECK: and_v8i16_i:
+
+ %1 = load <8 x i16>* %a
+ ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
+ %2 = and <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
+ ; CHECK-DAG: and.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
+ store <8 x i16> %2, <8 x i16>* %c
+ ; CHECK-DAG: st.h [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size and_v8i16_i
+}
+
+define void @and_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
+ ; CHECK: and_v4i32_i:
+
+ %1 = load <4 x i32>* %a
+ ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+ %2 = and <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
+ ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
+ ; CHECK-DAG: and.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
+ store <4 x i32> %2, <4 x i32>* %c
+ ; CHECK-DAG: st.w [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size and_v4i32_i
+}
+
+define void @and_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
+ ; CHECK: and_v2i64_i:
+
+ %1 = load <2 x i64>* %a
+ ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+ %2 = and <2 x i64> %1, <i64 1, i64 1>
+ ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
+ ; CHECK-DAG: and.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
+ store <2 x i64> %2, <2 x i64>* %c
+ ; CHECK-DAG: st.d [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size and_v2i64_i
+}
+
define void @or_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK: or_v16i8:
@@ -128,6 +187,65 @@ define void @or_v2i64(<2 x i64>* %c, <2
; CHECK: .size or_v2i64
}
+define void @or_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
+ ; CHECK: or_v16i8_i:
+
+ %1 = load <16 x i8>* %a
+ ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
+ %2 = or <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ ; CHECK-DAG: ori.b [[R4:\$w[0-9]+]], [[R1]], 1
+ store <16 x i8> %2, <16 x i8>* %c
+ ; CHECK-DAG: st.b [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size or_v16i8_i
+}
+
+define void @or_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
+ ; CHECK: or_v8i16_i:
+
+ %1 = load <8 x i16>* %a
+ ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
+ %2 = or <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
+ ; CHECK-DAG: or.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
+ store <8 x i16> %2, <8 x i16>* %c
+ ; CHECK-DAG: st.h [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size or_v8i16_i
+}
+
+define void @or_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
+ ; CHECK: or_v4i32_i:
+
+ %1 = load <4 x i32>* %a
+ ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+ %2 = or <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
+ ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
+ ; CHECK-DAG: or.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
+ store <4 x i32> %2, <4 x i32>* %c
+ ; CHECK-DAG: st.w [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size or_v4i32_i
+}
+
+define void @or_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
+ ; CHECK: or_v2i64_i:
+
+ %1 = load <2 x i64>* %a
+ ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+ %2 = or <2 x i64> %1, <i64 1, i64 1>
+ ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
+ ; CHECK-DAG: or.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
+ store <2 x i64> %2, <2 x i64>* %c
+ ; CHECK-DAG: st.d [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size or_v2i64_i
+}
+
define void @nor_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK: nor_v16i8:
@@ -196,6 +314,69 @@ define void @nor_v2i64(<2 x i64>* %c, <2
; CHECK: .size nor_v2i64
}
+define void @nor_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
+ ; CHECK: nor_v16i8_i:
+
+ %1 = load <16 x i8>* %a
+ ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
+ %2 = or <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ %3 = xor <16 x i8> %2, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+ ; CHECK-DAG: ori.b [[R4:\$w[0-9]+]], [[R1]], 1
+ store <16 x i8> %3, <16 x i8>* %c
+ ; CHECK-DAG: st.b [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size nor_v16i8_i
+}
+
+define void @nor_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
+ ; CHECK: nor_v8i16_i:
+
+ %1 = load <8 x i16>* %a
+ ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
+ %2 = or <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ %3 = xor <8 x i16> %2, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+ ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
+ ; CHECK-DAG: nor.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
+ store <8 x i16> %3, <8 x i16>* %c
+ ; CHECK-DAG: st.h [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size nor_v8i16_i
+}
+
+define void @nor_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
+ ; CHECK: nor_v4i32_i:
+
+ %1 = load <4 x i32>* %a
+ ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+ %2 = or <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
+ %3 = xor <4 x i32> %2, <i32 -1, i32 -1, i32 -1, i32 -1>
+ ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
+ ; CHECK-DAG: nor.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
+ store <4 x i32> %3, <4 x i32>* %c
+ ; CHECK-DAG: st.w [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size nor_v4i32_i
+}
+
+define void @nor_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
+ ; CHECK: nor_v2i64_i:
+
+ %1 = load <2 x i64>* %a
+ ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+ %2 = or <2 x i64> %1, <i64 1, i64 1>
+ %3 = xor <2 x i64> %2, <i64 -1, i64 -1>
+ ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
+ ; CHECK-DAG: nor.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
+ store <2 x i64> %3, <2 x i64>* %c
+ ; CHECK-DAG: st.d [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size nor_v2i64_i
+}
+
define void @xor_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK: xor_v16i8:
@@ -260,6 +441,65 @@ define void @xor_v2i64(<2 x i64>* %c, <2
; CHECK: .size xor_v2i64
}
+define void @xor_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
+ ; CHECK: xor_v16i8_i:
+
+ %1 = load <16 x i8>* %a
+ ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
+ %2 = xor <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ ; CHECK-DAG: xori.b [[R4:\$w[0-9]+]], [[R1]], 1
+ store <16 x i8> %2, <16 x i8>* %c
+ ; CHECK-DAG: st.b [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size xor_v16i8_i
+}
+
+define void @xor_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
+ ; CHECK: xor_v8i16_i:
+
+ %1 = load <8 x i16>* %a
+ ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
+ %2 = xor <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
+ ; CHECK-DAG: xor.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
+ store <8 x i16> %2, <8 x i16>* %c
+ ; CHECK-DAG: st.h [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size xor_v8i16_i
+}
+
+define void @xor_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
+ ; CHECK: xor_v4i32_i:
+
+ %1 = load <4 x i32>* %a
+ ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+ %2 = xor <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
+ ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
+ ; CHECK-DAG: xor.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
+ store <4 x i32> %2, <4 x i32>* %c
+ ; CHECK-DAG: st.w [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size xor_v4i32_i
+}
+
+define void @xor_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
+ ; CHECK: xor_v2i64_i:
+
+ %1 = load <2 x i64>* %a
+ ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+ %2 = xor <2 x i64> %1, <i64 1, i64 1>
+ ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
+ ; CHECK-DAG: xor.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
+ store <2 x i64> %2, <2 x i64>* %c
+ ; CHECK-DAG: st.d [[R4]], 0($4)
+
+ ret void
+ ; CHECK: .size xor_v2i64_i
+}
+
define void @sll_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK: sll_v16i8:
More information about the llvm-commits
mailing list