[llvm] r191156 - Correct the pre-increment load latencies in the PPC A2 itinerary

[Hal Finkel]

Author: hfinkel
Date: Sat Sep 21 19:08:14 2013
New Revision: 191156

URL: http://llvm.org/viewvc/llvm-project?rev=191156&view=rev
Log:
Correct the pre-increment load latencies in the PPC A2 itinerary

Pre-increment loads are microcoded on the A2, and the address increment occurs
only after the load completes. As a result, the latency of the GPR address
update is an additional 2 cycles on top of the load latency.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td

Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td?rev=191156&r1=191155&r2=191156&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td Sat Sep 21 19:08:14 2013
@@ -70,7 +70,7 @@ def PPCA2Itineraries : ProcessorItinerar
   InstrItinData<LdStLoad    , [InstrStage<1, [XU]>],
                               [6, 1, 1]>,
   InstrItinData<LdStLoadUpd , [InstrStage<1, [XU]>],
-                              [6, 2, 1, 1]>,
+                              [6, 8, 1, 1]>,
   InstrItinData<LdStLDU     , [InstrStage<1, [XU]>],
                               [6, 1, 1]>,
   InstrItinData<LdStStore   , [InstrStage<1, [XU]>],
@@ -86,11 +86,11 @@ def PPCA2Itineraries : ProcessorItinerar
   InstrItinData<LdStLFD     , [InstrStage<1, [XU]>],
                               [7, 1, 1]>,
   InstrItinData<LdStLFDU    , [InstrStage<1, [XU]>],
-                              [7, 2, 1, 1]>,
+                              [7, 9, 1, 1]>,
   InstrItinData<LdStLHA     , [InstrStage<1, [XU]>],
                               [6, 1, 1]>,
   InstrItinData<LdStLHAU    , [InstrStage<1, [XU]>],
-                              [6, 2, 1, 1]>,
+                              [6, 8, 1, 1]>,
   InstrItinData<LdStLWARX   , [InstrStage<1, [XU]>],
                               [82, 1, 1]>, // L2 latency
   InstrItinData<LdStSTD     , [InstrStage<1, [XU]>],