[llvm] r191130 - SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.
Renato Golin
renato.golin at linaro.org
Sat Sep 21 07:27:04 PDT 2013
Hi Jeuergen,
This commit introduced several compile time errors in our buildbot:
http://lab.llvm.org:8011/builders/clang-native-arm-lnt/builds/2845
Example:
fatal error: error in backend: Cannot select: 0x416c268: v4i16 =
ARMISD::VCGT 0x416c028, 0x416c1d8 [ORD=309] [ID=58]
0x416c028: v4i32 = or 0x41903a0, 0x416a7b0 [ORD=308] [ID=57]
0x41903a0: v4i32 = and 0x416af90, 0x416b608 [ORD=308] [ID=54]
0x416af90: v4i32 = ARMISD::VMVNIMM 0x416b4e8 [ORD=307] [ID=27]
0x416b4e8: i32 = TargetConstant<3199> [ID=18]
0x416b608: v4i32 = ARMISD::VCGT 0x416af90, 0x416a9f0 [ORD=307] [ID=53]
0x416af90: v4i32 = ARMISD::VMVNIMM 0x416b4e8 [ORD=307] [ID=27]
0x416b4e8: i32 = TargetConstant<3199> [ID=18]
0x416a9f0: v4i32 = add 0x416b968, 0x416b848 [ORD=306] [ID=52]
0x416b968: v4i32 = ARMISD::VSHRs 0x416b1d0, 0x416ac30 [ORD=305]
[ID=51]
0x416b1d0: v4i32 = add 0x416a690, 0x416bb18 [ORD=304] [ID=50]
0x416a690: v4i32 = ARMISD::VSHRs 0x416aba0, 0x416a720
[ORD=303] [ID=49]
0x416aba0: v4i32 = mul 0x416b2f0, 0x416b698 [ORD=302]
[ID=48]
0x416b2f0: v4i32 = sign_extend 0x416ab10 [ORD=301] [ID=47]
0x416b698: v4i32,ch = CopyFromReg 0x4011db8, 0x416b728
[ORD=302] [ID=23]
0x416a720: i32 = Constant<15> [ID=6]
0x416bb18: v4i32 = ARMISD::VMOVIMM 0x416bde8 [ORD=304] [ID=30]
0x416bde8: i32 = TargetConstant<1> [ID=20]
0x416ac30: i32 = Constant<1> [ID=7]
0x416b848: v4i32 = sign_extend 0x416be78 [ORD=299] [ID=46]
0x416be78: v4i16 = bitcast 0x416a450 [ORD=298] [ID=39]
0x416a450: f64,ch = load 0x4011db8, 0x416bf08,
0x416aa80<LD8[%lsr.iv4042](align=2)> [ORD=298] [ID=31]
0x416bf08: i32,ch = CopyFromReg 0x4011db8, 0x416b8d8
[ORD=295] [ID=21]
0x416b8d8: i32 = Register %vreg5 [ID=1]
0x416aa80: i32 = undef [ID=3]
0x416a7b0: v4i32 = and 0x416a9f0, 0x416a570 [ORD=308] [ID=56]
0x416a9f0: v4i32 = add 0x416b968, 0x416b848 [ORD=306] [ID=52]
0x416b968: v4i32 = ARMISD::VSHRs 0x416b1d0, 0x416ac30 [ORD=305]
[ID=51]
0x416b1d0: v4i32 = add 0x416a690, 0x416bb18 [ORD=304] [ID=50]
0x416a690: v4i32 = ARMISD::VSHRs 0x416aba0, 0x416a720 [ORD=303]
[ID=49]
0x416aba0: v4i32 = mul 0x416b2f0, 0x416b698 [ORD=302] [ID=48]
0x416b2f0: v4i32 = sign_extend 0x416ab10 [ORD=301] [ID=47]
0x416ab10: v4i16 = bitcast 0x4191000 [ORD=300] [ID=42]
0x416b698: v4i32,ch = CopyFromReg 0x4011db8, 0x416b728
[ORD=302] [ID=23]
0x416b728: v4i32 = Register %vreg2 [ID=5]
0x416a720: i32 = Constant<15> [ID=6]
0x416bb18: v4i32 = ARMISD::VMOVIMM 0x416bde8 [ORD=304] [ID=30]
0x416bde8: i32 = TargetConstant<1> [ID=20]
0x416ac30: i32 = Constant<1> [ID=7]
0x416b848: v4i32 = sign_extend 0x416be78 [ORD=299] [ID=46]
0x416be78: v4i16 = bitcast 0x416a450 [ORD=298] [ID=39]
0x416a450: f64,ch = load 0x4011db8, 0x416bf08,
0x416aa80<LD8[%lsr.iv4042](align=2)> [ORD=298] [ID=31]
0x416bf08: i32,ch = CopyFromReg 0x4011db8, 0x416b8d8
[ORD=295] [ID=21]
0x416b8d8: i32 = Register %vreg5 [ID=1]
0x416aa80: i32 = undef [ID=3]
0x416a570: v4i32 = xor 0x416b608, 0x4190700 [ORD=308] [ID=55]
0x416b608: v4i32 = ARMISD::VCGT 0x416af90, 0x416a9f0 [ORD=307]
[ID=53]
0x416af90: v4i32 = ARMISD::VMVNIMM 0x416b4e8 [ORD=307] [ID=27]
0x416b4e8: i32 = TargetConstant<3199> [ID=18]
0x416a9f0: v4i32 = add 0x416b968, 0x416b848 [ORD=306] [ID=52]
0x416b968: v4i32 = ARMISD::VSHRs 0x416b1d0, 0x416ac30 [ORD=305]
[ID=51]
0x416b1d0: v4i32 = add 0x416a690, 0x416bb18 [ORD=304] [ID=50]
0x416a690: v4i32 = ARMISD::VSHRs 0x416aba0, 0x416a720
[ORD=303] [ID=49]
0x416aba0: v4i32 = mul 0x416b2f0, 0x416b698 [ORD=302]
[ID=48]
0x416a720: i32 = Constant<15> [ID=6]
0x416bb18: v4i32 = ARMISD::VMOVIMM 0x416bde8 [ORD=304]
[ID=30]
0x416bde8: i32 = TargetConstant<1> [ID=20]
0x416ac30: i32 = Constant<1> [ID=7]
0x416b848: v4i32 = sign_extend 0x416be78 [ORD=299] [ID=46]
0x416be78: v4i16 = bitcast 0x416a450 [ORD=298] [ID=39]
0x416a450: f64,ch = load 0x4011db8, 0x416bf08,
0x416aa80<LD8[%lsr.iv4042](align=2)> [ORD=298] [ID=31]
0x416bf08: i32,ch = CopyFromReg 0x4011db8, 0x416b8d8
[ORD=295] [ID=21]
0x416aa80: i32 = undef [ID=3]
0x4190700: v4i32 = bitcast 0x4190670 [ID=36]
0x4190670: v16i8 = ARMISD::VMOVIMM 0x416b020 [ID=25]
0x416b020: i32 = TargetConstant<3839> [ID=17]
0x416c1d8: v4i32 = ARMISD::VMOVIMM 0x416b4e8 [ORD=309] [ID=28]
0x416b4e8: i32 = TargetConstant<3199> [ID=18]
In function: _Z5trainPsS_ii
On 21 September 2013 05:55, Juergen Ributzka <juergen at apple.com> wrote:
> Author: ributzka
> Date: Fri Sep 20 23:55:18 2013
> New Revision: 191130
>
> URL: http://llvm.org/viewvc/llvm-project?rev=191130&view=rev
> Log:
> SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs
> splitting too.
>
> The Type Legalizer recognizes that VSELECT needs to be split, because the
> type
> is to wide for the given target. The same does not always apply to SETCC,
> because less space is required to encode the result of a comparison. As a
> result
> VSELECT is split and SETCC is unrolled into scalar comparisons.
>
> This commit fixes the issue by checking for VSELECT-SETCC patterns in the
> DAG
> Combiner. If a matching pattern is found, then the result mask of SETCC is
> promoted to the expected vector mask for the given target. This mask has
> usually
> te same size as the VSELECT return type (except for Intel KNL). Now the
> type
> legalizer will split both VSELECT and SETCC.
>
> This allows the following X86 DAG Combine code to sucessfully detect the
> MIN/MAX
> pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>.
>
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