[llvm] r190929 - 'svn add' the test cases.
David Blaikie
dblaikie at gmail.com
Wed Sep 18 10:23:30 PDT 2013
On Wed, Sep 18, 2013 at 2:46 AM, Joey Gouly <joey.gouly at arm.com> wrote:
> Author: joey
> Date: Wed Sep 18 04:46:49 2013
> New Revision: 190929
>
> URL: http://llvm.org/viewvc/llvm-project?rev=190929&view=rev
> Log:
> 'svn add' the test cases.
>
Just for mailing list posterity, these test cases are for r190928.
>
> Added:
> llvm/trunk/test/MC/ARM/crc32-thumb.s
> llvm/trunk/test/MC/ARM/crc32.s
> llvm/trunk/test/MC/ARM/invalid-crc32.s
> llvm/trunk/test/MC/Disassembler/ARM/crc32-thumb.txt
> llvm/trunk/test/MC/Disassembler/ARM/crc32.txt
>
> Added: llvm/trunk/test/MC/ARM/crc32-thumb.s
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/crc32-thumb.s?rev=190929&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/crc32-thumb.s (added)
> +++ llvm/trunk/test/MC/ARM/crc32-thumb.s Wed Sep 18 04:46:49 2013
> @@ -0,0 +1,23 @@
> +@ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s | FileCheck %s
> +@ RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck
> %s --check-prefix=CHECK-V7
> + crc32b r0, r1, r2
> + crc32h r0, r1, r2
> + crc32w r0, r1, r2
> +
> +@ CHECK: crc32b r0, r1, r2 @ encoding:
> [0xc1,0xfa,0x82,0xf0]
> +@ CHECK: crc32h r0, r1, r2 @ encoding:
> [0xc1,0xfa,0x92,0xf0]
> +@ CHECK: crc32w r0, r1, r2 @ encoding:
> [0xc1,0xfa,0xa2,0xf0]
> +@ CHECK-V7: error: instruction requires: armv8
> +@ CHECK-V7: error: instruction requires: armv8
> +@ CHECK-V7: error: instruction requires: armv8
> +
> + crc32cb r0, r1, r2
> + crc32ch r0, r1, r2
> + crc32cw r0, r1, r2
> +
> +@ CHECK: crc32cb r0, r1, r2 @ encoding:
> [0xd1,0xfa,0x82,0xf0]
> +@ CHECK: crc32ch r0, r1, r2 @ encoding:
> [0xd1,0xfa,0x92,0xf0]
> +@ CHECK: crc32cw r0, r1, r2 @ encoding:
> [0xd1,0xfa,0xa2,0xf0]
> +@ CHECK-V7: error: instruction requires: armv8
> +@ CHECK-V7: error: instruction requires: armv8
> +@ CHECK-V7: error: instruction requires: armv8
>
> Added: llvm/trunk/test/MC/ARM/crc32.s
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/crc32.s?rev=190929&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/crc32.s (added)
> +++ llvm/trunk/test/MC/ARM/crc32.s Wed Sep 18 04:46:49 2013
> @@ -0,0 +1,23 @@
> +@ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s
> +@ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s
> --check-prefix=CHECK-V7
> + crc32b r0, r1, r2
> + crc32h r0, r1, r2
> + crc32w r0, r1, r2
> +
> +@ CHECK: crc32b r0, r1, r2 @ encoding:
> [0x42,0x00,0x01,0xe1]
> +@ CHECK: crc32h r0, r1, r2 @ encoding:
> [0x42,0x00,0x21,0xe1]
> +@ CHECK: crc32w r0, r1, r2 @ encoding:
> [0x42,0x00,0x41,0xe1]
> +@ CHECK-V7: error: instruction requires: armv8
> +@ CHECK-V7: error: instruction requires: armv8
> +@ CHECK-V7: error: instruction requires: armv8
> +
> + crc32cb r0, r1, r2
> + crc32ch r0, r1, r2
> + crc32cw r0, r1, r2
> +
> +@ CHECK: crc32cb r0, r1, r2 @ encoding:
> [0x42,0x02,0x01,0xe1]
> +@ CHECK: crc32ch r0, r1, r2 @ encoding:
> [0x42,0x02,0x21,0xe1]
> +@ CHECK: crc32cw r0, r1, r2 @ encoding:
> [0x42,0x02,0x41,0xe1]
> +@ CHECK-V7: error: instruction requires: armv8
> +@ CHECK-V7: error: instruction requires: armv8
> +@ CHECK-V7: error: instruction requires: armv8
>
> Added: llvm/trunk/test/MC/ARM/invalid-crc32.s
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/invalid-crc32.s?rev=190929&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/invalid-crc32.s (added)
> +++ llvm/trunk/test/MC/ARM/invalid-crc32.s Wed Sep 18 04:46:49 2013
> @@ -0,0 +1,16 @@
> +@ RUN: not llvm-mc -triple=armv8 -show-encoding < %s 2>&1 | FileCheck %s
> +@ RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck %s
> +
> + crc32cbeq r0, r1, r2
> + crc32bne r0, r1, r2
> + crc32chcc r0, r1, r2
> + crc32hpl r0, r1, r2
> + crc32cwgt r0, r1, r2
> + crc32wle r0, r1, r2
> +
> +@ CHECK: error: instruction 'crc32cb' is not predicable, but condition
> code specified
> +@ CHECK: error: instruction 'crc32b' is not predicable, but condition
> code specified
> +@ CHECK: error: instruction 'crc32ch' is not predicable, but condition
> code specified
> +@ CHECK: error: instruction 'crc32h' is not predicable, but condition
> code specified
> +@ CHECK: error: instruction 'crc32cw' is not predicable, but condition
> code specified
> +@ CHECK: error: instruction 'crc32w' is not predicable, but condition
> code specified
>
> Added: llvm/trunk/test/MC/Disassembler/ARM/crc32-thumb.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/crc32-thumb.txt?rev=190929&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/MC/Disassembler/ARM/crc32-thumb.txt (added)
> +++ llvm/trunk/test/MC/Disassembler/ARM/crc32-thumb.txt Wed Sep 18
> 04:46:49 2013
> @@ -0,0 +1,15 @@
> +# RUN: llvm-mc --disassemble %s -triple=thumbv8 2>&1 | FileCheck %s
> +
> +# CHECK: crc32b r0, r1, r2
> +# CHECK: crc32h r0, r1, r2
> +# CHECK: crc32w r0, r1, r2
> +# CHECK: crc32cb r0, r1, r2
> +# CHECK: crc32ch r0, r1, r2
> +# CHECK: crc32cw r0, r1, r2
> +
> +0xc1 0xfa 0x82 0xf0
> +0xc1 0xfa 0x92 0xf0
> +0xc1 0xfa 0xa2 0xf0
> +0xd1 0xfa 0x82 0xf0
> +0xd1 0xfa 0x92 0xf0
> +0xd1 0xfa 0xa2 0xf0
>
> Added: llvm/trunk/test/MC/Disassembler/ARM/crc32.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/crc32.txt?rev=190929&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/MC/Disassembler/ARM/crc32.txt (added)
> +++ llvm/trunk/test/MC/Disassembler/ARM/crc32.txt Wed Sep 18 04:46:49 2013
> @@ -0,0 +1,15 @@
> +# RUN: llvm-mc --disassemble %s -triple=armv8 2>&1 | FileCheck %s
> +
> +# CHECK: crc32b r0, r1, r2
> +# CHECK: crc32h r0, r1, r2
> +# CHECK: crc32w r0, r1, r2
> +# CHECK: crc32cb r0, r1, r2
> +# CHECK: crc32ch r0, r1, r2
> +# CHECK: crc32cw r0, r1, r2
> +
> +0x42 0x00 0x01 0xe1
> +0x42 0x00 0x21 0xe1
> +0x42 0x00 0x41 0xe1
> +0x42 0x02 0x01 0xe1
> +0x42 0x02 0x21 0xe1
> +0x42 0x02 0x41 0xe1
>
>
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