[llvm] r190793 - TableGen: give asm match classes deterministic order.

Tim Northover t.p.northover at gmail.com
Mon Sep 16 10:36:30 PDT 2013


> It would make my day if you could make the LessRegisterSet operator() const:

Very sorry about that. Done in r190797.

Tim.



More information about the llvm-commits mailing list