[llvm] r190717 - Adds support for Atom Silvermont (SLM) - -march=slm

[Gurd, Preston]

Just out of curiosity, when you have this:
+  InstrItinData<IIC_SHD16_REG_IM, [InstrStage<2, [IEC_RSV0]>] >,

do you intend this to mean that the shift occupied the IEC_RSV0 unit, and nothing else can use it for 2 cycles? Or you do mean that the latency is 2 cycles, but you can still issue back-to-back independent shifts?

 -Hal

For the above itinerary, I am trying to represent that this instruction must use the IEC reservation station 0 and that it will take two cycles to execute. I would like to also be able to represent that the throughput of the instruction is 2 cycles, but I do not know how to do this. 

Preston