[PATCH] AArch64: convert VPR64/VPR128 to RegisterOperands

[Tom Stellard]

On Thu, Sep 12, 2013 at 05:06:07AM -0700, Tim Northover wrote:
> This patch changes the AArch64 backend to use a RegisterOperand rather than a RegisterClass for the vector registers.
> 
> The difference is that RegisterOperands are essentially aliases for the RegisterClass with different printing/parsing methods. This matches almost exactly the status of AArch64's vector registers (they use "vN" in SIMD instructions but are really either "qN" or "dN").
> 
> Previously we had some rather nasty hierarchy of degenerate sub_xxx aliases, which Kevin Qin has recently discovered makes it virtually impossible to write patterns mapping VPR128 <-> VPR64.
> 
> Mostly this appears to simplify the code it touches. The main annoyance is that VPR128 and VPR64 become non-trivial operands and so the alias printer can't handle them (specifically, there's no way to print "mov vD.8b, vN.8b" instead of the "orr" form). However, this is an endemic problem (it already hits integer "mov" for example), so I think that's an acceptable sacrifice.
> 
> http://llvm-reviews.chandlerc.com/D1656
> 
> Index: lib/Target/AArch64/AArch64InstrNEON.td
> ===================================================================
> --- lib/Target/AArch64/AArch64InstrNEON.td
> +++ lib/Target/AArch64/AArch64InstrNEON.td
> @@ -2060,17 +2065,20 @@
>              (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
>  
>    def : Pat<(Neon_combine (v1i64 VPR64:$src),
> -              (v1i64 (bitconvert (v8i8 (op (v8i16 VPR128:$Rn), imm:$Imm))))),
> +                (v1i64 (bitconvert (v8i8 (op (v8i16 VPR128:$Rn), imm:$Imm))))),

I was looking at this patch and noticed a few whitespace changes.  I'm not
sure if this was done on purpose, but there's one here.

>              (!cast<Instruction>(prefix # "_16B")
> -              VPR64:$src, VPR128:$Rn, imm:$Imm)>;
> +                (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
> +                VPR128:$Rn, imm:$Imm)>;
>    def : Pat<(Neon_combine (v1i64 VPR64:$src),
> -              (v1i64 (bitconvert (v4i16 (op (v4i32 VPR128:$Rn), imm:$Imm))))),
> +                (v1i64 (bitconvert (v4i16 (op (v4i32 VPR128:$Rn), imm:$Imm))))),

Here

>              (!cast<Instruction>(prefix # "_8H")
> -              VPR64:$src, VPR128:$Rn, imm:$Imm)>;
> +                (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
> +                VPR128:$Rn, imm:$Imm)>;
>    def : Pat<(Neon_combine (v1i64 VPR64:$src),
> -              (v1i64 (bitconvert (v2i32 (op (v2i64 VPR128:$Rn), imm:$Imm))))),
> +                (v1i64 (bitconvert (v2i32 (op (v2i64 VPR128:$Rn), imm:$Imm))))),

Here too

>              (!cast<Instruction>(prefix # "_4S")
> -              VPR64:$src, VPR128:$Rn, imm:$Imm)>;
> +                  (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
> +                  VPR128:$Rn, imm:$Imm)>;
>  }
>  
>  defm : Neon_shiftNarrow_patterns<"lshr">;

-Tom