[PATCH] Partial support for Intel SHA Extensions (sha1rnds4)
Craig Topper
craig.topper at gmail.com
Wed Sep 11 22:13:25 PDT 2013
Comments inline.
On Wed, Sep 11, 2013 at 2:03 PM, Ben Langmuir <ben.langmuir at intel.com>wrote:
> Hi nadav,
>
> Add basic assembly/disassembly support for the first Intel SHA
> instruction 'sha1rnds4'. Also includes feature flag, and test cases.
>
> I've only included one instruction so that I can get early review as I
> have no
> experience with the instruction patterns in tablegen.
>
> Support for the remainin instructions will follow in a separate patch.
>
> http://llvm-reviews.chandlerc.com/D1650
>
> Files:
> lib/Target/X86/X86.td
> lib/Target/X86/X86InstrInfo.td
> lib/Target/X86/X86InstrSSE.td
> lib/Target/X86/X86Subtarget.cpp
> lib/Target/X86/X86Subtarget.h
> test/MC/Disassembler/X86/x86-64.txt
> test/MC/X86/x86_64-encoding.s
>
> Index: lib/Target/X86/X86.td
> ===================================================================
> --- lib/Target/X86/X86.td
> +++ lib/Target/X86/X86.td
> @@ -137,6 +137,8 @@
> "Support HLE">;
> def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
> "Support ADX instructions">;
> +def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
> + "Enable SHA instructions">;
>
Should imply FeatureSSE2 so that xmm registers are guaranteed valid.
> def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
> "Support PRFCHW instructions">;
> def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
> Index: lib/Target/X86/X86InstrInfo.td
> ===================================================================
> --- lib/Target/X86/X86InstrInfo.td
> +++ lib/Target/X86/X86InstrInfo.td
> @@ -675,6 +675,7 @@
> def HasHLE : Predicate<"Subtarget->hasHLE()">;
> def HasTSX : Predicate<"Subtarget->hasRTM() ||
> Subtarget->hasHLE()">;
> def HasADX : Predicate<"Subtarget->hasADX()">;
> +def HasSHA : Predicate<"Subtarget->hasSHA()">;
> def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
> def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
> def HasPrefetchW : Predicate<"Subtarget->has3DNow() ||
> Subtarget->hasPRFCHW()">;
> Index: lib/Target/X86/X86InstrSSE.td
> ===================================================================
> --- lib/Target/X86/X86InstrSSE.td
> +++ lib/Target/X86/X86InstrSSE.td
> @@ -7309,6 +7309,21 @@
> }
>
>
> //===----------------------------------------------------------------------===//
> +// SHA-NI Instructions
>
> +//===----------------------------------------------------------------------===//
> +
> +let hasSideEffects = 0, Predicates = [HasSHA] in {
> + def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
> + (ins VR128:$src1, i8imm:$src2),
> + "sha1rnds4\t{$src2, $src1, $dst|$dst, $src1,
> $src2}",
> + []>, TA;
> + def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
> + (ins f128mem:$src1, i8imm:$src2),
> + "sha1rnds4\t{$src2, $src1, $dst|$dst, $src1,
> $src2}",
> + []>, TA;
> +}
> +
>
Why f128mem and not i128mem?
Also believe that the dest is also an input so you need 2 input VR128 and a
constraint binding it to dest.
>
> +//===----------------------------------------------------------------------===//
> // AES-NI Instructions
>
> //===----------------------------------------------------------------------===//
>
> Index: lib/Target/X86/X86Subtarget.cpp
> ===================================================================
> --- lib/Target/X86/X86Subtarget.cpp
> +++ lib/Target/X86/X86Subtarget.cpp
> @@ -375,6 +375,10 @@
> HasCDI = true;
> ToggleFeature(X86::FeatureCDI);
> }
> + if (IsIntel && ((EBX >> 29) & 0x1)) {
> + HasSHA = true;
> + ToggleFeature(X86::FeatureSHA);
> + }
> }
> }
> }
> @@ -497,6 +501,7 @@
> HasCDI = false;
> HasPFI = false;
> HasADX = false;
> + HasSHA = false;
> HasPRFCHW = false;
> HasRDSEED = false;
> IsBTMemSlow = false;
> Index: lib/Target/X86/X86Subtarget.h
> ===================================================================
> --- lib/Target/X86/X86Subtarget.h
> +++ lib/Target/X86/X86Subtarget.h
> @@ -127,6 +127,9 @@
> /// HasADX - Processor has ADX instructions.
> bool HasADX;
>
> + /// HasSHA - Processor has SHA instructions.
> + bool HasSHA;
> +
> /// HasPRFCHW - Processor has PRFCHW instructions.
> bool HasPRFCHW;
>
> @@ -281,6 +284,7 @@
> bool hasRTM() const { return HasRTM; }
> bool hasHLE() const { return HasHLE; }
> bool hasADX() const { return HasADX; }
> + bool hasSHA() const { return HasSHA; }
> bool hasPRFCHW() const { return HasPRFCHW; }
> bool hasRDSEED() const { return HasRDSEED; }
> bool isBTMemSlow() const { return IsBTMemSlow; }
> Index: test/MC/Disassembler/X86/x86-64.txt
> ===================================================================
> --- test/MC/Disassembler/X86/x86-64.txt
> +++ test/MC/Disassembler/X86/x86-64.txt
> @@ -157,3 +157,9 @@
>
> # CHECK: movabsq %rax, -6066930261531658096
> 0x48 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
> +
> +# CHECK: sha1rnds4 $1, %xmm1, %xmm2
> +0x0f 0x3a 0xcc 0xd1 0x01
> +
> +# CHECK: sha1rnds4 $1, (%rax), %xmm2
> +0x0f 0x3a 0xcc 0x10 0x01
> \ No newline at end of file
> Index: test/MC/X86/x86_64-encoding.s
> ===================================================================
> --- test/MC/X86/x86_64-encoding.s
> +++ test/MC/X86/x86_64-encoding.s
> @@ -120,6 +120,14 @@
> // CHECK: fixup A - offset: 5, value: CPI1_0-4
> pshufb CPI1_0(%rip), %xmm1
>
> +// CHECK: sha1rnds4 $1, %xmm1, %xmm2
> +// CHECK: encoding: [0x0f,0x3a,0xcc,0xd1,0x01]
> +sha1rnds4 $1, %xmm1, %xmm2
> +
> +// CHECK: sha1rnds4 $1, (%rax), %xmm2
> +// CHECK: encoding: [0x0f,0x3a,0xcc,0x10,0x01]
> +sha1rnds4 $1, (%rax), %xmm2
> +
> // CHECK: movq 57005(,%riz), %rbx
> // CHECK: encoding: [0x48,0x8b,0x1c,0x25,0xad,0xde,0x00,0x00]
> movq 57005(,%riz), %rbx
>
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>
--
~Craig
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