[llvm] r190507 - [mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics)
Daniel Sanders
daniel.sanders at imgtec.com
Wed Sep 11 03:28:17 PDT 2013
Author: dsanders
Date: Wed Sep 11 05:28:16 2013
New Revision: 190507
URL: http://llvm.org/viewvc/llvm-project?rev=190507&view=rev
Log:
[mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics)
The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection.
Modified:
llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td?rev=190507&r1=190506&r2=190507&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td Wed Sep 11 05:28:16 2013
@@ -18,6 +18,7 @@ def MipsVAnyNonZero : SDNode<"MipsISD::V
def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
+// Immediates
def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>;
def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
@@ -980,14 +981,10 @@ class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"
class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d, MSA128D>,
IsCommutable;
-class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", int_mips_addv_b, MSA128B>,
- IsCommutable;
-class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", int_mips_addv_h, MSA128H>,
- IsCommutable;
-class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", int_mips_addv_w, MSA128W>,
- IsCommutable;
-class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", int_mips_addv_d, MSA128D>,
- IsCommutable;
+class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128B>, IsCommutable;
+class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128H>, IsCommutable;
+class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128W>, IsCommutable;
+class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128D>, IsCommutable;
class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", int_mips_addvi_b, MSA128B>;
class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", int_mips_addvi_h, MSA128H>;
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=190507&r1=190506&r2=190507&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp Wed Sep 11 05:28:16 2013
@@ -159,6 +159,7 @@ addMSAIntType(MVT::SimpleValueType Ty, c
setOperationAction(ISD::LOAD, Ty, Legal);
setOperationAction(ISD::STORE, Ty, Legal);
+ setOperationAction(ISD::ADD, Ty, Legal);
}
void MipsSETargetLowering::
@@ -799,6 +800,17 @@ static SDValue lowerDSPIntr(SDValue Op,
return DAG.getMergeValues(Vals, 2, DL);
}
+static SDValue lowerMSABinaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
+ SDLoc DL(Op);
+ SDValue LHS = Op->getOperand(1);
+ SDValue RHS = Op->getOperand(2);
+ EVT ResTy = Op->getValueType(0);
+
+ SDValue Result = DAG.getNode(Opc, DL, ResTy, LHS, RHS);
+
+ return Result;
+}
+
static SDValue lowerMSABranchIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
SDLoc DL(Op);
SDValue Value = Op->getOperand(1);
@@ -846,6 +858,11 @@ SDValue MipsSETargetLowering::lowerINTRI
return lowerDSPIntr(Op, DAG, MipsISD::MSub);
case Intrinsic::mips_msubu:
return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
+ case Intrinsic::mips_addv_b:
+ case Intrinsic::mips_addv_h:
+ case Intrinsic::mips_addv_w:
+ case Intrinsic::mips_addv_d:
+ return lowerMSABinaryIntr(Op, DAG, ISD::ADD);
case Intrinsic::mips_bnz_b:
case Intrinsic::mips_bnz_h:
case Intrinsic::mips_bnz_w:
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll?rev=190507&r1=190506&r2=190507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll Wed Sep 11 05:28:16 2013
@@ -443,6 +443,74 @@ declare <2 x i64> @llvm.mips.addv.d(<2 x
; CHECK: st.d
; CHECK: .size llvm_mips_addv_d_test
;
+
+define void @addv_b_test() nounwind {
+entry:
+ %0 = load <16 x i8>* @llvm_mips_addv_b_ARG1
+ %1 = load <16 x i8>* @llvm_mips_addv_b_ARG2
+ %2 = add <16 x i8> %0, %1
+ store <16 x i8> %2, <16 x i8>* @llvm_mips_addv_b_RES
+ ret void
+}
+
+; CHECK: addv_b_test:
+; CHECK: ld.b
+; CHECK: ld.b
+; CHECK: addv.b
+; CHECK: st.b
+; CHECK: .size addv_b_test
+;
+
+define void @addv_h_test() nounwind {
+entry:
+ %0 = load <8 x i16>* @llvm_mips_addv_h_ARG1
+ %1 = load <8 x i16>* @llvm_mips_addv_h_ARG2
+ %2 = add <8 x i16> %0, %1
+ store <8 x i16> %2, <8 x i16>* @llvm_mips_addv_h_RES
+ ret void
+}
+
+; CHECK: addv_h_test:
+; CHECK: ld.h
+; CHECK: ld.h
+; CHECK: addv.h
+; CHECK: st.h
+; CHECK: .size addv_h_test
+;
+
+define void @addv_w_test() nounwind {
+entry:
+ %0 = load <4 x i32>* @llvm_mips_addv_w_ARG1
+ %1 = load <4 x i32>* @llvm_mips_addv_w_ARG2
+ %2 = add <4 x i32> %0, %1
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_addv_w_RES
+ ret void
+}
+
+; CHECK: addv_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: addv.w
+; CHECK: st.w
+; CHECK: .size addv_w_test
+;
+
+define void @addv_d_test() nounwind {
+entry:
+ %0 = load <2 x i64>* @llvm_mips_addv_d_ARG1
+ %1 = load <2 x i64>* @llvm_mips_addv_d_ARG2
+ %2 = add <2 x i64> %0, %1
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_addv_d_RES
+ ret void
+}
+
+; CHECK: addv_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: addv.d
+; CHECK: st.d
+; CHECK: .size addv_d_test
+;
@llvm_mips_asub_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_asub_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
@llvm_mips_asub_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
More information about the llvm-commits
mailing list