[llvm] r190505 - [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics
Daniel Sanders
daniel.sanders at imgtec.com
Wed Sep 11 02:59:18 PDT 2013
Author: dsanders
Date: Wed Sep 11 04:59:17 2013
New Revision: 190505
URL: http://llvm.org/viewvc/llvm-project?rev=190505&view=rev
Log:
[mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics
The elements of the operands should be half the width of the elements of
the result.
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsMips.td
llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll
Modified: llvm/trunk/include/llvm/IR/IntrinsicsMips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsMips.td?rev=190505&r1=190504&r2=190505&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsMips.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsMips.td Wed Sep 11 04:59:17 2013
@@ -814,18 +814,18 @@ def int_mips_div_u_d : GCCBuiltin<"__bui
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
def int_mips_dotp_s_h : GCCBuiltin<"__builtin_msa_dotp_s_h">,
- Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
+ Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
def int_mips_dotp_s_w : GCCBuiltin<"__builtin_msa_dotp_s_w">,
- Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
+ Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
def int_mips_dotp_s_d : GCCBuiltin<"__builtin_msa_dotp_s_d">,
- Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
+ Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
def int_mips_dotp_u_h : GCCBuiltin<"__builtin_msa_dotp_u_h">,
- Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
+ Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
def int_mips_dotp_u_w : GCCBuiltin<"__builtin_msa_dotp_u_w">,
- Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
+ Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
def int_mips_dotp_u_d : GCCBuiltin<"__builtin_msa_dotp_u_d">,
- Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
+ Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
def int_mips_dpadd_s_h : GCCBuiltin<"__builtin_msa_dpadd_s_h">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty],
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td?rev=190505&r1=190504&r2=190505&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td Wed Sep 11 04:59:17 2013
@@ -1238,19 +1238,19 @@ class DIV_U_H_DESC : MSA_3R_DESC_BASE<"d
class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", int_mips_div_u_w, MSA128W>;
class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", int_mips_div_u_d, MSA128D>;
-class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, MSA128H>,
- IsCommutable;
-class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w, MSA128W>,
- IsCommutable;
-class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d, MSA128D>,
- IsCommutable;
+class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, MSA128H,
+ MSA128B, MSA128B>, IsCommutable;
+class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w, MSA128W,
+ MSA128H, MSA128H>, IsCommutable;
+class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d, MSA128D,
+ MSA128W, MSA128W>, IsCommutable;
-class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h, MSA128H>,
- IsCommutable;
-class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w, MSA128W>,
- IsCommutable;
-class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d, MSA128D>,
- IsCommutable;
+class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h, MSA128H,
+ MSA128B, MSA128B>, IsCommutable;
+class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w, MSA128W,
+ MSA128H, MSA128H>, IsCommutable;
+class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d, MSA128D,
+ MSA128W, MSA128W>, IsCommutable;
class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
MSA128H, MSA128B, MSA128B>,
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll?rev=190505&r1=190504&r2=190505&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll Wed Sep 11 04:59:17 2013
@@ -179,134 +179,168 @@ declare <2 x i64> @llvm.mips.div.u.d(<2
; CHECK: st.d
; CHECK: .size llvm_mips_div_u_d_test
;
- at llvm_mips_dotp_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
- at llvm_mips_dotp_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
- at llvm_mips_dotp_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
+ at llvm_mips_dotp_s_h_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3,
+ i8 4, i8 5, i8 6, i8 7,
+ i8 8, i8 9, i8 10, i8 11,
+ i8 12, i8 13, i8 14, i8 15>,
+ align 16
+ at llvm_mips_dotp_s_h_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19,
+ i8 20, i8 21, i8 22, i8 23,
+ i8 24, i8 25, i8 26, i8 27,
+ i8 28, i8 29, i8 30, i8 31>,
+ align 16
+ at llvm_mips_dotp_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0,
+ i16 0, i16 0, i16 0, i16 0>,
+ align 16
define void @llvm_mips_dotp_s_h_test() nounwind {
entry:
- %0 = load <8 x i16>* @llvm_mips_dotp_s_h_ARG1
- %1 = load <8 x i16>* @llvm_mips_dotp_s_h_ARG2
- %2 = tail call <8 x i16> @llvm.mips.dotp.s.h(<8 x i16> %0, <8 x i16> %1)
+ %0 = load <16 x i8>* @llvm_mips_dotp_s_h_ARG1
+ %1 = load <16 x i8>* @llvm_mips_dotp_s_h_ARG2
+ %2 = tail call <8 x i16> @llvm.mips.dotp.s.h(<16 x i8> %0, <16 x i8> %1)
store <8 x i16> %2, <8 x i16>* @llvm_mips_dotp_s_h_RES
ret void
}
-declare <8 x i16> @llvm.mips.dotp.s.h(<8 x i16>, <8 x i16>) nounwind
+declare <8 x i16> @llvm.mips.dotp.s.h(<16 x i8>, <16 x i8>) nounwind
; CHECK: llvm_mips_dotp_s_h_test:
-; CHECK: ld.h
-; CHECK: ld.h
+; CHECK: ld.b
+; CHECK: ld.b
; CHECK: dotp_s.h
; CHECK: st.h
; CHECK: .size llvm_mips_dotp_s_h_test
;
- at llvm_mips_dotp_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
- at llvm_mips_dotp_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
- at llvm_mips_dotp_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+ at llvm_mips_dotp_s_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3,
+ i16 4, i16 5, i16 6, i16 7>,
+ align 16
+ at llvm_mips_dotp_s_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7,
+ i16 8, i16 9, i16 10, i16 11>,
+ align 16
+ at llvm_mips_dotp_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>,
+ align 16
define void @llvm_mips_dotp_s_w_test() nounwind {
entry:
- %0 = load <4 x i32>* @llvm_mips_dotp_s_w_ARG1
- %1 = load <4 x i32>* @llvm_mips_dotp_s_w_ARG2
- %2 = tail call <4 x i32> @llvm.mips.dotp.s.w(<4 x i32> %0, <4 x i32> %1)
+ %0 = load <8 x i16>* @llvm_mips_dotp_s_w_ARG1
+ %1 = load <8 x i16>* @llvm_mips_dotp_s_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.dotp.s.w(<8 x i16> %0, <8 x i16> %1)
store <4 x i32> %2, <4 x i32>* @llvm_mips_dotp_s_w_RES
ret void
}
-declare <4 x i32> @llvm.mips.dotp.s.w(<4 x i32>, <4 x i32>) nounwind
+declare <4 x i32> @llvm.mips.dotp.s.w(<8 x i16>, <8 x i16>) nounwind
; CHECK: llvm_mips_dotp_s_w_test:
-; CHECK: ld.w
-; CHECK: ld.w
+; CHECK: ld.h
+; CHECK: ld.h
; CHECK: dotp_s.w
; CHECK: st.w
; CHECK: .size llvm_mips_dotp_s_w_test
;
- at llvm_mips_dotp_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
- at llvm_mips_dotp_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
+ at llvm_mips_dotp_s_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 0, i32 1>,
+ align 16
+ at llvm_mips_dotp_s_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 2, i32 3>,
+ align 16
@llvm_mips_dotp_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
define void @llvm_mips_dotp_s_d_test() nounwind {
entry:
- %0 = load <2 x i64>* @llvm_mips_dotp_s_d_ARG1
- %1 = load <2 x i64>* @llvm_mips_dotp_s_d_ARG2
- %2 = tail call <2 x i64> @llvm.mips.dotp.s.d(<2 x i64> %0, <2 x i64> %1)
+ %0 = load <4 x i32>* @llvm_mips_dotp_s_d_ARG1
+ %1 = load <4 x i32>* @llvm_mips_dotp_s_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.dotp.s.d(<4 x i32> %0, <4 x i32> %1)
store <2 x i64> %2, <2 x i64>* @llvm_mips_dotp_s_d_RES
ret void
}
-declare <2 x i64> @llvm.mips.dotp.s.d(<2 x i64>, <2 x i64>) nounwind
+declare <2 x i64> @llvm.mips.dotp.s.d(<4 x i32>, <4 x i32>) nounwind
; CHECK: llvm_mips_dotp_s_d_test:
-; CHECK: ld.d
-; CHECK: ld.d
+; CHECK: ld.w
+; CHECK: ld.w
; CHECK: dotp_s.d
; CHECK: st.d
; CHECK: .size llvm_mips_dotp_s_d_test
;
- at llvm_mips_dotp_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
- at llvm_mips_dotp_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
- at llvm_mips_dotp_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
+ at llvm_mips_dotp_u_h_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3,
+ i8 4, i8 5, i8 6, i8 7,
+ i8 8, i8 9, i8 10, i8 11,
+ i8 12, i8 13, i8 14, i8 15>,
+ align 16
+ at llvm_mips_dotp_u_h_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19,
+ i8 20, i8 21, i8 22, i8 23,
+ i8 24, i8 25, i8 26, i8 27,
+ i8 28, i8 29, i8 30, i8 31>,
+ align 16
+ at llvm_mips_dotp_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0,
+ i16 0, i16 0, i16 0, i16 0>,
+ align 16
define void @llvm_mips_dotp_u_h_test() nounwind {
entry:
- %0 = load <8 x i16>* @llvm_mips_dotp_u_h_ARG1
- %1 = load <8 x i16>* @llvm_mips_dotp_u_h_ARG2
- %2 = tail call <8 x i16> @llvm.mips.dotp.u.h(<8 x i16> %0, <8 x i16> %1)
+ %0 = load <16 x i8>* @llvm_mips_dotp_u_h_ARG1
+ %1 = load <16 x i8>* @llvm_mips_dotp_u_h_ARG2
+ %2 = tail call <8 x i16> @llvm.mips.dotp.u.h(<16 x i8> %0, <16 x i8> %1)
store <8 x i16> %2, <8 x i16>* @llvm_mips_dotp_u_h_RES
ret void
}
-declare <8 x i16> @llvm.mips.dotp.u.h(<8 x i16>, <8 x i16>) nounwind
+declare <8 x i16> @llvm.mips.dotp.u.h(<16 x i8>, <16 x i8>) nounwind
; CHECK: llvm_mips_dotp_u_h_test:
-; CHECK: ld.h
-; CHECK: ld.h
+; CHECK: ld.b
+; CHECK: ld.b
; CHECK: dotp_u.h
; CHECK: st.h
; CHECK: .size llvm_mips_dotp_u_h_test
;
- at llvm_mips_dotp_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
- at llvm_mips_dotp_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
- at llvm_mips_dotp_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+ at llvm_mips_dotp_u_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3,
+ i16 4, i16 5, i16 6, i16 7>,
+ align 16
+ at llvm_mips_dotp_u_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7,
+ i16 8, i16 9, i16 10, i16 11>,
+ align 16
+ at llvm_mips_dotp_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>,
+ align 16
define void @llvm_mips_dotp_u_w_test() nounwind {
entry:
- %0 = load <4 x i32>* @llvm_mips_dotp_u_w_ARG1
- %1 = load <4 x i32>* @llvm_mips_dotp_u_w_ARG2
- %2 = tail call <4 x i32> @llvm.mips.dotp.u.w(<4 x i32> %0, <4 x i32> %1)
+ %0 = load <8 x i16>* @llvm_mips_dotp_u_w_ARG1
+ %1 = load <8 x i16>* @llvm_mips_dotp_u_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.dotp.u.w(<8 x i16> %0, <8 x i16> %1)
store <4 x i32> %2, <4 x i32>* @llvm_mips_dotp_u_w_RES
ret void
}
-declare <4 x i32> @llvm.mips.dotp.u.w(<4 x i32>, <4 x i32>) nounwind
+declare <4 x i32> @llvm.mips.dotp.u.w(<8 x i16>, <8 x i16>) nounwind
; CHECK: llvm_mips_dotp_u_w_test:
-; CHECK: ld.w
-; CHECK: ld.w
+; CHECK: ld.h
+; CHECK: ld.h
; CHECK: dotp_u.w
; CHECK: st.w
; CHECK: .size llvm_mips_dotp_u_w_test
;
- at llvm_mips_dotp_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
- at llvm_mips_dotp_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
+ at llvm_mips_dotp_u_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 0, i32 1>,
+ align 16
+ at llvm_mips_dotp_u_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 2, i32 3>,
+ align 16
@llvm_mips_dotp_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
define void @llvm_mips_dotp_u_d_test() nounwind {
entry:
- %0 = load <2 x i64>* @llvm_mips_dotp_u_d_ARG1
- %1 = load <2 x i64>* @llvm_mips_dotp_u_d_ARG2
- %2 = tail call <2 x i64> @llvm.mips.dotp.u.d(<2 x i64> %0, <2 x i64> %1)
+ %0 = load <4 x i32>* @llvm_mips_dotp_u_d_ARG1
+ %1 = load <4 x i32>* @llvm_mips_dotp_u_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.dotp.u.d(<4 x i32> %0, <4 x i32> %1)
store <2 x i64> %2, <2 x i64>* @llvm_mips_dotp_u_d_RES
ret void
}
-declare <2 x i64> @llvm.mips.dotp.u.d(<2 x i64>, <2 x i64>) nounwind
+declare <2 x i64> @llvm.mips.dotp.u.d(<4 x i32>, <4 x i32>) nounwind
; CHECK: llvm_mips_dotp_u_d_test:
-; CHECK: ld.d
-; CHECK: ld.d
+; CHECK: ld.w
+; CHECK: ld.w
; CHECK: dotp_u.d
; CHECK: st.d
; CHECK: .size llvm_mips_dotp_u_d_test
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