[llvm] r190219 - [mips] Set instruction itineraries of loads, stores and conditional moves.
Akira Hatanaka
ahatanaka at mips.com
Fri Sep 6 16:28:25 PDT 2013
Author: ahatanak
Date: Fri Sep 6 18:28:24 2013
New Revision: 190219
URL: http://llvm.org/viewvc/llvm-project?rev=190219&view=rev
Log:
[mips] Set instruction itineraries of loads, stores and conditional moves.
Modified:
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsCondMov.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
llvm/trunk/test/MC/Mips/xgot.ll
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=190219&r1=190218&r2=190219&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Fri Sep 6 18:28:24 2013
@@ -135,16 +135,16 @@ def SD : Store<"sd", GPR64Opnd, store
/// load/store left/right
let isCodeGenOnly = 1 in {
-def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd>, LW_FM<0x22>;
-def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd>, LW_FM<0x26>;
-def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd>, LW_FM<0x2a>;
-def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd>, LW_FM<0x2e>;
+def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, IILoad>, LW_FM<0x22>;
+def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, IILoad>, LW_FM<0x26>;
+def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, IIStore>, LW_FM<0x2a>;
+def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, IIStore>, LW_FM<0x2e>;
}
-def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd>, LW_FM<0x1a>;
-def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd>, LW_FM<0x1b>;
-def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd>, LW_FM<0x2c>;
-def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd>, LW_FM<0x2d>;
+def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, IILoad>, LW_FM<0x1a>;
+def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, IILoad>, LW_FM<0x1b>;
+def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, IIStore>, LW_FM<0x2c>;
+def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, IIStore>, LW_FM<0x2d>;
/// Load-linked, Store-conditional
def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>;
Modified: llvm/trunk/lib/Target/Mips/MipsCondMov.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCondMov.td?rev=190219&r1=190218&r2=190219&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsCondMov.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsCondMov.td Fri Sep 6 18:28:24 2013
@@ -103,28 +103,28 @@ multiclass MovnPats<RegisterClass CRC, R
}
// Instantiation of instructions.
-def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, NoItinerary>,
+def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, IIArith>,
ADD_FM<0, 0xa>;
let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
- def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd,
- NoItinerary>, ADD_FM<0, 0xa>;
- def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd,
- NoItinerary>, ADD_FM<0, 0xa>;
- def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd,
- NoItinerary>, ADD_FM<0, 0xa>;
+ def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, IIArith>,
+ ADD_FM<0, 0xa>;
+ def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, IIArith>,
+ ADD_FM<0, 0xa>;
+ def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, IIArith>,
+ ADD_FM<0, 0xa>;
}
-def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
- NoItinerary>, ADD_FM<0, 0xb>;
+def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, IIArith>,
+ ADD_FM<0, 0xb>;
let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
- def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd,
- NoItinerary>, ADD_FM<0, 0xb>;
- def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd,
- NoItinerary>, ADD_FM<0, 0xb>;
- def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd,
- NoItinerary>, ADD_FM<0, 0xb>;
+ def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, IIArith>,
+ ADD_FM<0, 0xb>;
+ def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, IIArith>,
+ ADD_FM<0, 0xb>;
+ def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, IIArith>,
+ ADD_FM<0, 0xb>;
}
def MOVZ_I_S : CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, IIFmove>,
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=190219&r1=190218&r2=190219&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Sep 6 18:28:24 2013
@@ -461,7 +461,7 @@ class FMem<bits<6> op, dag outs, dag ins
class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
- [(set RO:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI, opstr> {
+ [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
let DecoderMethod = "DecodeMem";
let canFoldAsLoad = 1;
let mayLoad = 1;
@@ -470,24 +470,26 @@ class Load<string opstr, DAGOperand RO,
class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
- [(OpNode RO:$rt, Addr:$addr)], NoItinerary, FrmI, opstr> {
+ [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
let DecoderMethod = "DecodeMem";
let mayStore = 1;
}
// Load/Store Left/Right
let canFoldAsLoad = 1 in
-class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> :
+class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
+ InstrItinClass Itin> :
InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
!strconcat(opstr, "\t$rt, $addr"),
- [(set RO:$rt, (OpNode addr:$addr, RO:$src))], NoItinerary, FrmI> {
+ [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
let DecoderMethod = "DecodeMem";
string Constraints = "$src = $rt";
}
-class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> :
+class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
+ InstrItinClass Itin> :
InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
- [(OpNode RO:$rt, addr:$addr)], NoItinerary, FrmI> {
+ [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
let DecoderMethod = "DecodeMem";
}
@@ -925,10 +927,10 @@ def SH : Store<"sh", GPR32Opnd, truncst
def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
/// load/store left/right
-def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd>, LW_FM<0x22>;
-def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd>, LW_FM<0x26>;
-def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd>, LW_FM<0x2a>;
-def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd>, LW_FM<0x2e>;
+def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>;
+def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>;
+def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>;
+def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>;
def SYNC : SYNC_FT, SYNC_FM;
def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=190219&r1=190218&r2=190219&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll Fri Sep 6 18:28:24 2013
@@ -10,22 +10,23 @@
define void @f1() nounwind {
entry:
-; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1)
-; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1)
-; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]])
-; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]])
-; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]])
-; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]])
-; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]])
-; CHECK: sw $[[R6]], 36($sp)
-; CHECK: sw $[[R5]], 32($sp)
-; CHECK: sw $[[R4]], 28($sp)
-; CHECK: sw $[[R3]], 24($sp)
-; CHECK: sw $[[R7]], 20($sp)
-; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]])
-; CHECK: sw $[[R2]], 16($sp)
-; CHECK: lw $6, %lo(f1.s1)($[[R1]])
-; CHECK: lw $7, 4($[[R0]])
+; CHECK-LABEL: f1:
+; CHECK-DAG: lw $[[R1:[0-9]+]], %got(f1.s1)
+; CHECK-DAG: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1)
+; CHECK-DAG: lw $[[R7:[0-9]+]], 12($[[R0]])
+; CHECK-DAG: lw $[[R3:[0-9]+]], 16($[[R0]])
+; CHECK-DAG: lw $[[R4:[0-9]+]], 20($[[R0]])
+; CHECK-DAG: lw $[[R5:[0-9]+]], 24($[[R0]])
+; CHECK-DAG: lw $[[R6:[0-9]+]], 28($[[R0]])
+; CHECK-DAG: sw $[[R6]], 36($sp)
+; CHECK-DAG: sw $[[R5]], 32($sp)
+; CHECK-DAG: sw $[[R4]], 28($sp)
+; CHECK-DAG: sw $[[R3]], 24($sp)
+; CHECK-DAG: sw $[[R7]], 20($sp)
+; CHECK-DAG: lw $[[R2:[0-9]+]], 8($[[R0]])
+; CHECK-DAG: sw $[[R2]], 16($sp)
+; CHECK-DAG: lw $6, %lo(f1.s1)($[[R1]])
+; CHECK-DAG: lw $7, 4($[[R0]])
%agg.tmp10 = alloca %struct.S3, align 4
call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
call void @callee2(%struct.S2* byval @f1.s2) nounwind
Modified: llvm/trunk/test/MC/Mips/xgot.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/xgot.ll?rev=190219&r1=190218&r2=190219&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/xgot.ll (original)
+++ llvm/trunk/test/MC/Mips/xgot.ll Fri Sep 6 18:28:24 2013
@@ -14,10 +14,10 @@ entry:
; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_LO16
; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT_HI16
; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT_LO16
-; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT
-; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_LO16
; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_CALL_HI16
; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_CALL_LO16
+; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT
+; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_LO16
; CHECK: ]
%0 = load i32* @ext_1, align 4
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