[llvm] r190148 - This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
Vladimir Medic
Vladimir.Medic at imgtec.com
Fri Sep 6 05:41:17 PDT 2013
Author: vmedic
Date: Fri Sep 6 07:41:17 2013
New Revision: 190148
URL: http://llvm.org/viewvc/llvm-project?rev=190148&view=rev
Log:
This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
Added:
llvm/trunk/test/MC/Mips/micromips-movcond-instructions.s
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsCondMov.td
llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
llvm/trunk/test/MC/Disassembler/Mips/micromips.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td?rev=190148&r1=190147&r2=190148&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td Fri Sep 6 07:41:17 2013
@@ -123,3 +123,18 @@ class LWL_FM_MM<bits<4> funct> {
let Inst{15-12} = funct;
let Inst{11-0} = addr{11-0};
}
+
+class CMov_F_I_FM_MM<bits<7> func> : MMArch {
+ bits<5> rd;
+ bits<5> rs;
+ bits<3> fcc;
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0x15;
+ let Inst{25-21} = rd;
+ let Inst{20-16} = rs;
+ let Inst{15-13} = fcc;
+ let Inst{12-6} = func;
+ let Inst{5-0} = 0x3b;
+}
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=190148&r1=190147&r2=190148&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Fri Sep 6 07:41:17 2013
@@ -109,4 +109,14 @@ let DecoderNamespace = "MicroMips", Pred
LWL_FM_MM<0x8>;
def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
LWL_FM_MM<0x9>;
+
+ /// Move Conditional
+ def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
+ NoItinerary>, ADD_FM_MM<0, 0x58>;
+ def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
+ NoItinerary>, ADD_FM_MM<0, 0x18>;
+ def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, IIAlu>,
+ CMov_F_I_FM_MM<0x25>;
+ def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, IIAlu>,
+ CMov_F_I_FM_MM<0x5>;
}
Modified: llvm/trunk/lib/Target/Mips/MipsCondMov.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCondMov.td?rev=190148&r1=190147&r2=190148&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsCondMov.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsCondMov.td Fri Sep 6 07:41:17 2013
@@ -19,7 +19,7 @@
class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
InstrItinClass Itin> :
InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
- !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR> {
+ !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> {
let Constraints = "$F = $rd";
}
@@ -37,7 +37,7 @@ class CMov_F_I_FT<string opstr, Register
InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
!strconcat(opstr, "\t$rd, $rs, $fcc"),
[(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
- Itin, FrmFR> {
+ Itin, FrmFR, opstr> {
let Constraints = "$F = $rd";
}
@@ -103,7 +103,7 @@ multiclass MovnPats<RegisterClass CRC, R
}
// Instantiation of instructions.
-def MOVZ_I_I : CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, NoItinerary>,
+def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, NoItinerary>,
ADD_FM<0, 0xa>;
let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
@@ -115,8 +115,8 @@ let Predicates = [HasStdEnc], isCodeGenO
NoItinerary>, ADD_FM<0, 0xa>;
}
-def MOVN_I_I : CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
- NoItinerary>, ADD_FM<0, 0xb>;
+def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
+ NoItinerary>, ADD_FM<0, 0xb>;
let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd,
@@ -161,14 +161,14 @@ let Predicates = [IsFP64bit, HasStdEnc],
}
}
-def MOVT_I : CMov_F_I_FT<"movt", GPR32Opnd, IIArith, MipsCMovFP_T>,
+def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, IIArith, MipsCMovFP_T>,
CMov_F_I_FM<1>;
let isCodeGenOnly = 1 in
def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, IIArith, MipsCMovFP_T>,
CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]>;
-def MOVF_I : CMov_F_I_FT<"movf", GPR32Opnd, IIArith, MipsCMovFP_F>,
+def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, IIArith, MipsCMovFP_F>,
CMov_F_I_FM<0>;
let isCodeGenOnly = 1 in
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=190148&r1=190147&r2=190148&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Fri Sep 6 07:41:17 2013
@@ -730,7 +730,7 @@ class CMov_I_F_FM<bits<6> funct, bits<5>
let Inst{5-0} = funct;
}
-class CMov_F_I_FM<bit tf> {
+class CMov_F_I_FM<bit tf> : StdArch {
bits<5> rd;
bits<5> rs;
bits<3> fcc;
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips.txt?rev=190148&r1=190147&r2=190148&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips.txt Fri Sep 6 07:41:17 2013
@@ -147,3 +147,15 @@
# CHECK: swr $4, 16($5)
0x60 0x85 0x90 0x10
+
+# CHECK: movz $9, $6, $7
+0x00 0xe6 0x48 0x58
+
+# CHECK: movn $9, $6, $7
+0x00 0xe6 0x48 0x18
+
+# CHECK: movt $9, $6, $fcc0
+0x55 0x26 0x09 0x7b
+
+# CHECK: movf $9, $6, $fcc0
+0x55 0x26 0x01 0x7b
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt?rev=190148&r1=190147&r2=190148&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt Fri Sep 6 07:41:17 2013
@@ -147,3 +147,15 @@
# CHECK: swr $4, 16($5)
0x85 0x60 0x10 0x90
+
+# CHECK: movz $9, $6, $7
+0xe6 0x00 0x58 0x48
+
+# CHECK: movn $9, $6, $7
+0xe6 0x00 0x18 0x48
+
+# CHECK: movt $9, $6, $fcc0
+0x26 0x55 0x7b 0x09
+
+# CHECK: movf $9, $6, $fcc0
+0x26 0x55 0x7b 0x01
Added: llvm/trunk/test/MC/Mips/micromips-movcond-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-movcond-instructions.s?rev=190148&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-movcond-instructions.s (added)
+++ llvm/trunk/test/MC/Mips/micromips-movcond-instructions.s Fri Sep 6 07:41:17 2013
@@ -0,0 +1,26 @@
+# RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips \
+# RUN: | FileCheck -check-prefix=CHECK-EL %s
+# RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips \
+# RUN: | FileCheck -check-prefix=CHECK-EB %s
+# Check that the assembler can handle the documented syntax
+# for move conditional instructions.
+#------------------------------------------------------------------------------
+# Move Conditional
+#------------------------------------------------------------------------------
+# Little endian
+#------------------------------------------------------------------------------
+# CHECK-EL: movz $9, $6, $7 # encoding: [0xe6,0x00,0x58,0x48]
+# CHECK-EL: movn $9, $6, $7 # encoding: [0xe6,0x00,0x18,0x48]
+# CHECK-EL: movt $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x09]
+# CHECK-EL: movf $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x01]
+#------------------------------------------------------------------------------
+# Big endian
+#------------------------------------------------------------------------------
+# CHECK-EB: movz $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x58]
+# CHECK-EB: movn $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x18]
+# CHECK-EB: movt $9, $6, $fcc0 # encoding: [0x55,0x26,0x09,0x7b]
+# CHECK-EB: movf $9, $6, $fcc0 # encoding: [0x55,0x26,0x01,0x7b]
+ movz $9, $6, $7
+ movn $9, $6, $7
+ movt $9, $6, $fcc0
+ movf $9, $6, $fcc0
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