[llvm] r189961 - Swift: Only build vldm/vstm with q register aligned register lists

Arnold Schwaighofer aschwaighofer at apple.com
Wed Sep 4 10:41:16 PDT 2013


Author: arnolds
Date: Wed Sep  4 12:41:16 2013
New Revision: 189961

URL: http://llvm.org/viewvc/llvm-project?rev=189961&view=rev
Log:
Swift: Only build vldm/vstm with q register aligned register lists

Unaligned vldm/vstm need more uops and therefore are slower in general on swift.

radar://14522102

Added:
    llvm/trunk/test/CodeGen/ARM/swift-vldm.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=189961&r1=189960&r2=189961&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Wed Sep  4 12:41:16 2013
@@ -489,7 +489,10 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBas
     if (Reg != ARM::SP &&
         NewOffset == Offset + (int)Size &&
         ((isNotVFP && RegNum > PRegNum) ||
-         ((Count < Limit) && RegNum == PRegNum+1))) {
+         ((Count < Limit) && RegNum == PRegNum+1)) &&
+        // On Swift we don't want vldm/vstm to start with a odd register num
+        // because Q register unaligned vldm/vstm need more uops.
+        (!STI->isSwift() || isNotVFP || Count != 1 || !(PRegNum & 0x1))) {
       Offset += Size;
       PRegNum = RegNum;
       ++Count;

Added: llvm/trunk/test/CodeGen/ARM/swift-vldm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/swift-vldm.ll?rev=189961&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/swift-vldm.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/swift-vldm.ll Wed Sep  4 12:41:16 2013
@@ -0,0 +1,28 @@
+; RUN: llc < %s -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck %s
+
+; vldm with registers not aligned with q registers need more micro-ops so that
+; so that there usage becomes unbeneficial on swift.
+
+; CHECK-LABEL: test_vldm
+; CHECK: vldmia  r1, {d18, d19, d20}
+; CHECK-NOT: vldmia  r1, {d17, d18, d19, d20}
+
+define double @test_vldm(double %a, double %b, double* nocapture %x) {
+entry:
+  %mul73 = fmul double %a, %b
+  %addr1 = getelementptr double * %x, i32 1
+  %addr2 = getelementptr double * %x, i32 2
+  %addr3 = getelementptr double * %x, i32 3
+  %load0 = load double * %x
+  %load1 = load double * %addr1
+  %load2 = load double * %addr2
+  %load3 = load double * %addr3
+  %sub = fsub double %mul73, %load1
+  %mul = fmul double %mul73, %load0
+  %add = fadd double %mul73, %load2
+  %div = fdiv double %mul73, %load3
+  %red = fadd double %sub, %mul
+  %red2 = fadd double %div, %add
+  %red3 = fsub double %red, %red2
+  ret double %red3
+}





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