[llvm] r189483 - ARM: Use "dmb sy" for barriers on M-class CPUs

[Tim Northover]

Author: tnorthover
Date: Wed Aug 28 09:39:19 2013
New Revision: 189483

URL: http://llvm.org/viewvc/llvm-project?rev=189483&view=rev
Log:
ARM: Use "dmb sy" for barriers on M-class CPUs

The usual default of "dmb ish" (inner-shareable) isn't even a valid instruction
on v6M or v7M (well, it does the same thing but software is strongly
discouraged from using it) so we should emit a full-system barrier there.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/Thumb/barrier.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=189483&r1=189482&r2=189483&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Aug 28 09:39:19 2013
@@ -2600,7 +2600,10 @@ static SDValue LowerATOMIC_FENCE(SDValue
   ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
   AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
   unsigned Domain = ARM_MB::ISH;
-  if (Subtarget->isSwift() && Ord == Release) {
+  if (Subtarget->isMClass()) {
+    // Only a full system barrier exists in the M-class architectures.
+    Domain = ARM_MB::SY;
+  } else if (Subtarget->isSwift() && Ord == Release) {
     // Swift happens to implement ISHST barriers in a way that's compatible with
     // Release semantics but weaker than ISH so we'd be fools not to use
     // it. Beware: other processors probably don't!

Modified: llvm/trunk/test/CodeGen/Thumb/barrier.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/barrier.ll?rev=189483&r1=189482&r2=189483&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/barrier.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/barrier.ll Wed Aug 28 09:39:19 2013
@@ -7,7 +7,7 @@ define void @t1() {
 ; V6: blx {{_*}}sync_synchronize
 
 ; V6M-LABEL: t1:
-; V6M: dmb ish
+; V6M: dmb sy
   fence seq_cst
   ret void
 }