[llvm] r189467 - [mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri
Daniel Sanders
daniel.sanders at imgtec.com
Wed Aug 28 03:12:09 PDT 2013
Author: dsanders
Date: Wed Aug 28 05:12:09 2013
New Revision: 189467
URL: http://llvm.org/viewvc/llvm-project?rev=189467&view=rev
Log:
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsMips.td
llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll
llvm/trunk/test/CodeGen/Mips/msa/bit.ll
Modified: llvm/trunk/include/llvm/IR/IntrinsicsMips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsMips.td?rev=189467&r1=189466&r2=189467&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsMips.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsMips.td Wed Aug 28 05:12:09 2013
@@ -846,6 +846,11 @@ def int_mips_fadd_w : GCCBuiltin<"__buil
def int_mips_fadd_d : GCCBuiltin<"__builtin_msa_fadd_d">,
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+def int_mips_fcaf_w : GCCBuiltin<"__builtin_msa_fcaf_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
+def int_mips_fcaf_d : GCCBuiltin<"__builtin_msa_fcaf_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+
def int_mips_fceq_w : GCCBuiltin<"__builtin_msa_fceq_w">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
def int_mips_fceq_d : GCCBuiltin<"__builtin_msa_fceq_d">,
@@ -871,11 +876,36 @@ def int_mips_fcne_w : GCCBuiltin<"__buil
def int_mips_fcne_d : GCCBuiltin<"__builtin_msa_fcne_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+def int_mips_fcor_w : GCCBuiltin<"__builtin_msa_fcor_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
+def int_mips_fcor_d : GCCBuiltin<"__builtin_msa_fcor_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+
+def int_mips_fcueq_w : GCCBuiltin<"__builtin_msa_fcueq_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
+def int_mips_fcueq_d : GCCBuiltin<"__builtin_msa_fcueq_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+
+def int_mips_fcule_w : GCCBuiltin<"__builtin_msa_fcule_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
+def int_mips_fcule_d : GCCBuiltin<"__builtin_msa_fcule_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+
+def int_mips_fcult_w : GCCBuiltin<"__builtin_msa_fcult_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
+def int_mips_fcult_d : GCCBuiltin<"__builtin_msa_fcult_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+
def int_mips_fcun_w : GCCBuiltin<"__builtin_msa_fcun_w">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
def int_mips_fcun_d : GCCBuiltin<"__builtin_msa_fcun_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+def int_mips_fcune_w : GCCBuiltin<"__builtin_msa_fcune_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
+def int_mips_fcune_d : GCCBuiltin<"__builtin_msa_fcune_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+
def int_mips_fdiv_w : GCCBuiltin<"__builtin_msa_fdiv_w">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
def int_mips_fdiv_d : GCCBuiltin<"__builtin_msa_fdiv_d">,
@@ -983,6 +1013,11 @@ def int_mips_frsqrt_w : GCCBuiltin<"__bu
def int_mips_frsqrt_d : GCCBuiltin<"__builtin_msa_frsqrt_d">,
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], []>;
+def int_mips_fsaf_w : GCCBuiltin<"__builtin_msa_fsaf_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
+def int_mips_fsaf_d : GCCBuiltin<"__builtin_msa_fsaf_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+
def int_mips_fseq_w : GCCBuiltin<"__builtin_msa_fseq_w">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
def int_mips_fseq_d : GCCBuiltin<"__builtin_msa_fseq_d">,
@@ -1003,6 +1038,11 @@ def int_mips_fsne_w : GCCBuiltin<"__buil
def int_mips_fsne_d : GCCBuiltin<"__builtin_msa_fsne_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+def int_mips_fsor_w : GCCBuiltin<"__builtin_msa_fsor_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
+def int_mips_fsor_d : GCCBuiltin<"__builtin_msa_fsor_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+
def int_mips_fsqrt_w : GCCBuiltin<"__builtin_msa_fsqrt_w">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], []>;
def int_mips_fsqrt_d : GCCBuiltin<"__builtin_msa_fsqrt_d">,
@@ -1013,6 +1053,31 @@ def int_mips_fsub_w : GCCBuiltin<"__buil
def int_mips_fsub_d : GCCBuiltin<"__builtin_msa_fsub_d">,
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+def int_mips_fsueq_w : GCCBuiltin<"__builtin_msa_fsueq_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
+def int_mips_fsueq_d : GCCBuiltin<"__builtin_msa_fsueq_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+
+def int_mips_fsule_w : GCCBuiltin<"__builtin_msa_fsule_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
+def int_mips_fsule_d : GCCBuiltin<"__builtin_msa_fsule_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+
+def int_mips_fsult_w : GCCBuiltin<"__builtin_msa_fsult_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
+def int_mips_fsult_d : GCCBuiltin<"__builtin_msa_fsult_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+
+def int_mips_fsun_w : GCCBuiltin<"__builtin_msa_fsun_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
+def int_mips_fsun_d : GCCBuiltin<"__builtin_msa_fsun_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+
+def int_mips_fsune_w : GCCBuiltin<"__builtin_msa_fsune_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
+def int_mips_fsune_d : GCCBuiltin<"__builtin_msa_fsune_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+
def int_mips_ftint_s_w : GCCBuiltin<"__builtin_msa_ftint_s_w">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], []>;
def int_mips_ftint_s_d : GCCBuiltin<"__builtin_msa_ftint_s_d">,
@@ -1028,6 +1093,44 @@ def int_mips_ftq_h : GCCBuiltin<"__built
def int_mips_ftq_w : GCCBuiltin<"__builtin_msa_ftq_w">,
Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], []>;
+def int_mips_ftrunc_s_w : GCCBuiltin<"__builtin_msa_ftrunc_s_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], []>;
+def int_mips_ftrunc_s_d : GCCBuiltin<"__builtin_msa_ftrunc_s_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty], []>;
+
+def int_mips_ftrunc_u_w : GCCBuiltin<"__builtin_msa_ftrunc_u_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], []>;
+def int_mips_ftrunc_u_d : GCCBuiltin<"__builtin_msa_ftrunc_u_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty], []>;
+
+def int_mips_hadd_s_h : GCCBuiltin<"__builtin_msa_hadd_s_h">,
+ Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
+def int_mips_hadd_s_w : GCCBuiltin<"__builtin_msa_hadd_s_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
+def int_mips_hadd_s_d : GCCBuiltin<"__builtin_msa_hadd_s_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
+
+def int_mips_hadd_u_h : GCCBuiltin<"__builtin_msa_hadd_u_h">,
+ Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
+def int_mips_hadd_u_w : GCCBuiltin<"__builtin_msa_hadd_u_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
+def int_mips_hadd_u_d : GCCBuiltin<"__builtin_msa_hadd_u_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
+
+def int_mips_hsub_s_h : GCCBuiltin<"__builtin_msa_hsub_s_h">,
+ Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
+def int_mips_hsub_s_w : GCCBuiltin<"__builtin_msa_hsub_s_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
+def int_mips_hsub_s_d : GCCBuiltin<"__builtin_msa_hsub_s_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
+
+def int_mips_hsub_u_h : GCCBuiltin<"__builtin_msa_hsub_u_h">,
+ Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
+def int_mips_hsub_u_w : GCCBuiltin<"__builtin_msa_hsub_u_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
+def int_mips_hsub_u_d : GCCBuiltin<"__builtin_msa_hsub_u_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
+
def int_mips_ilvev_b : GCCBuiltin<"__builtin_msa_ilvev_b">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
def int_mips_ilvev_h : GCCBuiltin<"__builtin_msa_ilvev_h">,
@@ -1435,6 +1538,24 @@ def int_mips_srai_w : GCCBuiltin<"__buil
def int_mips_srai_d : GCCBuiltin<"__builtin_msa_srai_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
+def int_mips_srar_b : GCCBuiltin<"__builtin_msa_srar_b">,
+ Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
+def int_mips_srar_h : GCCBuiltin<"__builtin_msa_srar_h">,
+ Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
+def int_mips_srar_w : GCCBuiltin<"__builtin_msa_srar_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
+def int_mips_srar_d : GCCBuiltin<"__builtin_msa_srar_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
+
+def int_mips_srari_b : GCCBuiltin<"__builtin_msa_srari_b">,
+ Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
+def int_mips_srari_h : GCCBuiltin<"__builtin_msa_srari_h">,
+ Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
+def int_mips_srari_w : GCCBuiltin<"__builtin_msa_srari_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
+def int_mips_srari_d : GCCBuiltin<"__builtin_msa_srari_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
+
def int_mips_srl_b : GCCBuiltin<"__builtin_msa_srl_b">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
def int_mips_srl_h : GCCBuiltin<"__builtin_msa_srl_h">,
@@ -1453,6 +1574,24 @@ def int_mips_srli_w : GCCBuiltin<"__buil
def int_mips_srli_d : GCCBuiltin<"__builtin_msa_srli_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
+def int_mips_srlr_b : GCCBuiltin<"__builtin_msa_srlr_b">,
+ Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
+def int_mips_srlr_h : GCCBuiltin<"__builtin_msa_srlr_h">,
+ Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
+def int_mips_srlr_w : GCCBuiltin<"__builtin_msa_srlr_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
+def int_mips_srlr_d : GCCBuiltin<"__builtin_msa_srlr_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
+
+def int_mips_srlri_b : GCCBuiltin<"__builtin_msa_srlri_b">,
+ Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
+def int_mips_srlri_h : GCCBuiltin<"__builtin_msa_srlri_h">,
+ Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
+def int_mips_srlri_w : GCCBuiltin<"__builtin_msa_srlri_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
+def int_mips_srlri_d : GCCBuiltin<"__builtin_msa_srlri_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
+
def int_mips_subs_s_b : GCCBuiltin<"__builtin_msa_subs_s_b">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [Commutative]>;
def int_mips_subs_s_h : GCCBuiltin<"__builtin_msa_subs_s_h">,
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td?rev=189467&r1=189466&r2=189467&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td Wed Aug 28 05:12:09 2013
@@ -258,6 +258,9 @@ class DPSUB_U_D_ENC : MSA_3R_FMT<0b101,
class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
+class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
+class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
+
class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
@@ -270,12 +273,27 @@ class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0
class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
-class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
-class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
+class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
+class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
+
+class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
+class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
+
+class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
+class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
+
+class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
+class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
+
+class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
+class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
+class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
+class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
+
class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
@@ -340,6 +358,9 @@ class FRCP_D_ENC : MSA_2RF_FMT<0b1100101
class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
+class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
+class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
+
class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
@@ -349,8 +370,11 @@ class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0
class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
-class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
-class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
+class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
+class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
+
+class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
+class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
@@ -358,6 +382,27 @@ class FSQRT_D_ENC : MSA_2RF_FMT<0b110010
class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
+class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
+class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
+
+class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
+class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
+
+class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
+class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
+
+class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
+class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
+
+class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
+class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
+
+class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110100000, 0b0, 0b011110>;
+class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110100000, 0b1, 0b011110>;
+
+class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110100001, 0b0, 0b011110>;
+class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110100001, 0b1, 0b011110>;
+
class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
@@ -367,6 +412,22 @@ class FTINT_U_D_ENC : MSA_2RF_FMT<0b1100
class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
+class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
+class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
+class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
+
+class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
+class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
+class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
+
+class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
+class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
+class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
+
+class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
+class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
+class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
+
class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
@@ -406,11 +467,11 @@ class LDI_H_ENC : MSA_I10_FMT<0b010, 0
class LDI_W_ENC : MSA_I10_FMT<0b010, 0b10, 0b001100>;
class LDI_D_ENC : MSA_I10_FMT<0b010, 0b11, 0b001100>;
-class MADD_Q_H_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
-class MADD_Q_W_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
+class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
+class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
-class MADDR_Q_H_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
-class MADDR_Q_W_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
+class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
+class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
@@ -477,11 +538,11 @@ class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b
class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
-class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
-class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
+class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
+class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
-class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
-class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
+class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
+class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
@@ -491,8 +552,8 @@ class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b
class MUL_Q_H_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011100>;
class MUL_Q_W_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011100>;
-class MULR_Q_H_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
-class MULR_Q_W_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
+class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
+class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
@@ -586,6 +647,16 @@ class SRAI_H_ENC : MSA_BIT_H_FMT<0b001,
class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
+class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
+class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
+class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
+class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
+
+class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
+class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
+class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
+class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
+
class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
@@ -596,6 +667,16 @@ class SRLI_H_ENC : MSA_BIT_H_FMT<0b010,
class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
+class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
+class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
+class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
+class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
+
+class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
+class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
+class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
+class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
+
class ST_B_ENC : MSA_I5_FMT<0b111, 0b00, 0b000111>;
class ST_H_ENC : MSA_I5_FMT<0b111, 0b01, 0b000111>;
class ST_W_ENC : MSA_I5_FMT<0b111, 0b10, 0b000111>;
@@ -1245,6 +1326,13 @@ class FADD_D_DESC : MSA_3RF_DESC_BASE<"f
NoItinerary, MSA128D, MSA128D>,
IsCommutable;
+class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w,
+ NoItinerary, MSA128W, MSA128W>,
+ IsCommutable;
+class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d,
+ NoItinerary, MSA128D, MSA128D>,
+ IsCommutable;
+
class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", int_mips_fceq_w,
NoItinerary, MSA128W, MSA128W>,
IsCommutable;
@@ -1274,6 +1362,34 @@ class FCNE_D_DESC : MSA_3RF_DESC_BASE<"f
NoItinerary, MSA128D, MSA128D>,
IsCommutable;
+class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", int_mips_fcor_w,
+ NoItinerary, MSA128W, MSA128W>,
+ IsCommutable;
+class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", int_mips_fcor_d,
+ NoItinerary, MSA128D, MSA128D>,
+ IsCommutable;
+
+class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", int_mips_fcueq_w,
+ NoItinerary, MSA128W, MSA128W>,
+ IsCommutable;
+class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", int_mips_fcueq_d,
+ NoItinerary, MSA128D, MSA128D>,
+ IsCommutable;
+
+class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", int_mips_fcule_w,
+ NoItinerary, MSA128W, MSA128W>,
+ IsCommutable;
+class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", int_mips_fcule_d,
+ NoItinerary, MSA128D, MSA128D>,
+ IsCommutable;
+
+class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", int_mips_fcult_w,
+ NoItinerary, MSA128W, MSA128W>,
+ IsCommutable;
+class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", int_mips_fcult_d,
+ NoItinerary, MSA128D, MSA128D>,
+ IsCommutable;
+
class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", int_mips_fcun_w,
NoItinerary, MSA128W, MSA128W>,
IsCommutable;
@@ -1281,6 +1397,13 @@ class FCUN_D_DESC : MSA_3RF_DESC_BASE<"f
NoItinerary, MSA128D, MSA128D>,
IsCommutable;
+class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", int_mips_fcune_w,
+ NoItinerary, MSA128W, MSA128W>,
+ IsCommutable;
+class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", int_mips_fcune_d,
+ NoItinerary, MSA128D, MSA128D>,
+ IsCommutable;
+
class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", int_mips_fdiv_w,
NoItinerary, MSA128W, MSA128W>;
class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", int_mips_fdiv_d,
@@ -1388,6 +1511,11 @@ class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<
class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
NoItinerary, MSA128D, MSA128D>;
+class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w,
+ NoItinerary, MSA128W, MSA128W>;
+class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d,
+ NoItinerary, MSA128D, MSA128D>;
+
class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w,
NoItinerary, MSA128W, MSA128W>;
class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d,
@@ -1408,6 +1536,11 @@ class FSNE_W_DESC : MSA_3RF_DESC_BASE<"f
class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d,
NoItinerary, MSA128D, MSA128D>;
+class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w,
+ NoItinerary, MSA128W, MSA128W>;
+class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d,
+ NoItinerary, MSA128D, MSA128D>;
+
class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", int_mips_fsqrt_w,
NoItinerary, MSA128W, MSA128W>;
class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", int_mips_fsqrt_d,
@@ -1418,6 +1551,41 @@ class FSUB_W_DESC : MSA_3RF_DESC_BASE<"f
class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", int_mips_fsub_d,
NoItinerary, MSA128D, MSA128D>;
+class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
+ NoItinerary, MSA128W, MSA128W>;
+class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
+ NoItinerary, MSA128D, MSA128D>;
+
+class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
+ NoItinerary, MSA128W, MSA128W>;
+class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
+ NoItinerary, MSA128D, MSA128D>;
+
+class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
+ NoItinerary, MSA128W, MSA128W>;
+class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
+ NoItinerary, MSA128D, MSA128D>;
+
+class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
+ NoItinerary, MSA128W, MSA128W>;
+class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
+ NoItinerary, MSA128D, MSA128D>;
+
+class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
+ NoItinerary, MSA128W, MSA128W>;
+class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
+ NoItinerary, MSA128D, MSA128D>;
+
+class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", int_mips_ftrunc_s_w,
+ NoItinerary, MSA128W, MSA128W>;
+class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", int_mips_ftrunc_s_d,
+ NoItinerary, MSA128D, MSA128D>;
+
+class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", int_mips_ftrunc_u_w,
+ NoItinerary, MSA128W, MSA128W>;
+class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", int_mips_ftrunc_u_d,
+ NoItinerary, MSA128D, MSA128D>;
+
class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
NoItinerary, MSA128W, MSA128W>;
class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
@@ -1433,6 +1601,34 @@ class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ft
class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
NoItinerary, MSA128W, MSA128D>;
+class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
+ NoItinerary, MSA128H, MSA128B>;
+class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
+ NoItinerary, MSA128W, MSA128H>;
+class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
+ NoItinerary, MSA128D, MSA128W>;
+
+class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
+ NoItinerary, MSA128H, MSA128B>;
+class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
+ NoItinerary, MSA128W, MSA128H>;
+class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
+ NoItinerary, MSA128D, MSA128W>;
+
+class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
+ NoItinerary, MSA128H, MSA128B>;
+class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
+ NoItinerary, MSA128W, MSA128H>;
+class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
+ NoItinerary, MSA128D, MSA128W>;
+
+class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
+ NoItinerary, MSA128H, MSA128B>;
+class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
+ NoItinerary, MSA128W, MSA128H>;
+class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
+ NoItinerary, MSA128D, MSA128W>;
+
class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", int_mips_ilvev_b, NoItinerary,
MSA128B, MSA128B>;
class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", int_mips_ilvev_h, NoItinerary,
@@ -1828,6 +2024,24 @@ class SRAI_W_DESC : MSA_BIT_W_DESC_BASE<
class SRAI_D_DESC : MSA_BIT_D_DESC_BASE<"srai.d", int_mips_srai_d,
NoItinerary, MSA128D, MSA128D>;
+class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, NoItinerary,
+ MSA128B, MSA128B>;
+class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, NoItinerary,
+ MSA128H, MSA128H>;
+class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, NoItinerary,
+ MSA128W, MSA128W>;
+class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, NoItinerary,
+ MSA128D, MSA128D>;
+
+class SRARI_B_DESC : MSA_BIT_B_DESC_BASE<"srari.b", int_mips_srari_b,
+ NoItinerary, MSA128B, MSA128B>;
+class SRARI_H_DESC : MSA_BIT_H_DESC_BASE<"srari.h", int_mips_srari_h,
+ NoItinerary, MSA128H, MSA128H>;
+class SRARI_W_DESC : MSA_BIT_W_DESC_BASE<"srari.w", int_mips_srari_w,
+ NoItinerary, MSA128W, MSA128W>;
+class SRARI_D_DESC : MSA_BIT_D_DESC_BASE<"srari.d", int_mips_srari_d,
+ NoItinerary, MSA128D, MSA128D>;
+
class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", int_mips_srl_b, NoItinerary,
MSA128B, MSA128B>;
class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", int_mips_srl_h, NoItinerary,
@@ -1846,6 +2060,24 @@ class SRLI_W_DESC : MSA_BIT_W_DESC_BASE<
class SRLI_D_DESC : MSA_BIT_D_DESC_BASE<"srli.d", int_mips_srli_d,
NoItinerary, MSA128D, MSA128D>;
+class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, NoItinerary,
+ MSA128B, MSA128B>;
+class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, NoItinerary,
+ MSA128H, MSA128H>;
+class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, NoItinerary,
+ MSA128W, MSA128W>;
+class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, NoItinerary,
+ MSA128D, MSA128D>;
+
+class SRLRI_B_DESC : MSA_BIT_B_DESC_BASE<"srlri.b", int_mips_srlri_b,
+ NoItinerary, MSA128B, MSA128B>;
+class SRLRI_H_DESC : MSA_BIT_H_DESC_BASE<"srlri.h", int_mips_srlri_h,
+ NoItinerary, MSA128H, MSA128H>;
+class SRLRI_W_DESC : MSA_BIT_W_DESC_BASE<"srlri.w", int_mips_srlri_w,
+ NoItinerary, MSA128W, MSA128W>;
+class SRLRI_D_DESC : MSA_BIT_D_DESC_BASE<"srlri.d", int_mips_srlri_d,
+ NoItinerary, MSA128D, MSA128D>;
+
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, InstrItinClass itin, RegisterClass RCWD,
Operand MemOpnd = mem, ComplexPattern Addr = addr> {
@@ -2154,6 +2386,9 @@ def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D
def FADD_W : FADD_W_ENC, FADD_W_DESC, Requires<[HasMSA]>;
def FADD_D : FADD_D_ENC, FADD_D_DESC, Requires<[HasMSA]>;
+def FCAF_W : FCAF_W_ENC, FCAF_W_DESC, Requires<[HasMSA]>;
+def FCAF_D : FCAF_D_ENC, FCAF_D_DESC, Requires<[HasMSA]>;
+
def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC, Requires<[HasMSA]>;
def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC, Requires<[HasMSA]>;
@@ -2169,9 +2404,24 @@ def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DE
def FCNE_W : FCNE_W_ENC, FCNE_W_DESC, Requires<[HasMSA]>;
def FCNE_D : FCNE_D_ENC, FCNE_D_DESC, Requires<[HasMSA]>;
+def FCOR_W : FCOR_W_ENC, FCOR_W_DESC, Requires<[HasMSA]>;
+def FCOR_D : FCOR_D_ENC, FCOR_D_DESC, Requires<[HasMSA]>;
+
+def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC, Requires<[HasMSA]>;
+def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC, Requires<[HasMSA]>;
+
+def FCULE_W : FCULE_W_ENC, FCULE_W_DESC, Requires<[HasMSA]>;
+def FCULE_D : FCULE_D_ENC, FCULE_D_DESC, Requires<[HasMSA]>;
+
+def FCULT_W : FCULT_W_ENC, FCULT_W_DESC, Requires<[HasMSA]>;
+def FCULT_D : FCULT_D_ENC, FCULT_D_DESC, Requires<[HasMSA]>;
+
def FCUN_W : FCUN_W_ENC, FCUN_W_DESC, Requires<[HasMSA]>;
def FCUN_D : FCUN_D_ENC, FCUN_D_DESC, Requires<[HasMSA]>;
+def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC, Requires<[HasMSA]>;
+def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC, Requires<[HasMSA]>;
+
def FDIV_W : FDIV_W_ENC, FDIV_W_DESC, Requires<[HasMSA]>;
def FDIV_D : FDIV_D_ENC, FDIV_D_DESC, Requires<[HasMSA]>;
@@ -2236,6 +2486,9 @@ def FRCP_D : FRCP_D_ENC, FRCP_D_DESC, Re
def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC, Requires<[HasMSA]>;
def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC, Requires<[HasMSA]>;
+def FSAF_W : FSAF_W_ENC, FSAF_W_DESC, Requires<[HasMSA]>;
+def FSAF_D : FSAF_D_ENC, FSAF_D_DESC, Requires<[HasMSA]>;
+
def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC, Requires<[HasMSA]>;
def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC, Requires<[HasMSA]>;
@@ -2248,12 +2501,36 @@ def FSLT_D : FSLT_D_ENC, FSLT_D_DESC, Re
def FSNE_W : FSNE_W_ENC, FSNE_W_DESC, Requires<[HasMSA]>;
def FSNE_D : FSNE_D_ENC, FSNE_D_DESC, Requires<[HasMSA]>;
+def FSOR_W : FSOR_W_ENC, FSOR_W_DESC, Requires<[HasMSA]>;
+def FSOR_D : FSOR_D_ENC, FSOR_D_DESC, Requires<[HasMSA]>;
+
def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC, Requires<[HasMSA]>;
def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC, Requires<[HasMSA]>;
def FSUB_W : FSUB_W_ENC, FSUB_W_DESC, Requires<[HasMSA]>;
def FSUB_D : FSUB_D_ENC, FSUB_D_DESC, Requires<[HasMSA]>;
+def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC, Requires<[HasMSA]>;
+def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC, Requires<[HasMSA]>;
+
+def FSULE_W : FSULE_W_ENC, FSULE_W_DESC, Requires<[HasMSA]>;
+def FSULE_D : FSULE_D_ENC, FSULE_D_DESC, Requires<[HasMSA]>;
+
+def FSULT_W : FSULT_W_ENC, FSULT_W_DESC, Requires<[HasMSA]>;
+def FSULT_D : FSULT_D_ENC, FSULT_D_DESC, Requires<[HasMSA]>;
+
+def FSUN_W : FSUN_W_ENC, FSUN_W_DESC, Requires<[HasMSA]>;
+def FSUN_D : FSUN_D_ENC, FSUN_D_DESC, Requires<[HasMSA]>;
+
+def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC, Requires<[HasMSA]>;
+def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC, Requires<[HasMSA]>;
+
+def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC, Requires<[HasMSA]>;
+def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC, Requires<[HasMSA]>;
+
+def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC, Requires<[HasMSA]>;
+def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC, Requires<[HasMSA]>;
+
def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC, Requires<[HasMSA]>;
def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC, Requires<[HasMSA]>;
@@ -2263,6 +2540,22 @@ def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D
def FTQ_H : FTQ_H_ENC, FTQ_H_DESC, Requires<[HasMSA]>;
def FTQ_W : FTQ_W_ENC, FTQ_W_DESC, Requires<[HasMSA]>;
+def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC, Requires<[HasMSA]>;
+def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC, Requires<[HasMSA]>;
+def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC, Requires<[HasMSA]>;
+
+def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC, Requires<[HasMSA]>;
+def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC, Requires<[HasMSA]>;
+def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC, Requires<[HasMSA]>;
+
+def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC, Requires<[HasMSA]>;
+def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC, Requires<[HasMSA]>;
+def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC, Requires<[HasMSA]>;
+
+def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC, Requires<[HasMSA]>;
+def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC, Requires<[HasMSA]>;
+def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC, Requires<[HasMSA]>;
+
def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC, Requires<[HasMSA]>;
def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC, Requires<[HasMSA]>;
def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC, Requires<[HasMSA]>;
@@ -2481,6 +2774,16 @@ def SRAI_H : SRAI_H_ENC, SRAI_H_DESC, Re
def SRAI_W : SRAI_W_ENC, SRAI_W_DESC, Requires<[HasMSA]>;
def SRAI_D : SRAI_D_ENC, SRAI_D_DESC, Requires<[HasMSA]>;
+def SRAR_B : SRAR_B_ENC, SRAR_B_DESC, Requires<[HasMSA]>;
+def SRAR_H : SRAR_H_ENC, SRAR_H_DESC, Requires<[HasMSA]>;
+def SRAR_W : SRAR_W_ENC, SRAR_W_DESC, Requires<[HasMSA]>;
+def SRAR_D : SRAR_D_ENC, SRAR_D_DESC, Requires<[HasMSA]>;
+
+def SRARI_B : SRARI_B_ENC, SRARI_B_DESC, Requires<[HasMSA]>;
+def SRARI_H : SRARI_H_ENC, SRARI_H_DESC, Requires<[HasMSA]>;
+def SRARI_W : SRARI_W_ENC, SRARI_W_DESC, Requires<[HasMSA]>;
+def SRARI_D : SRARI_D_ENC, SRARI_D_DESC, Requires<[HasMSA]>;
+
def SRL_B : SRL_B_ENC, SRL_B_DESC, Requires<[HasMSA]>;
def SRL_H : SRL_H_ENC, SRL_H_DESC, Requires<[HasMSA]>;
def SRL_W : SRL_W_ENC, SRL_W_DESC, Requires<[HasMSA]>;
@@ -2491,6 +2794,16 @@ def SRLI_H : SRLI_H_ENC, SRLI_H_DESC, Re
def SRLI_W : SRLI_W_ENC, SRLI_W_DESC, Requires<[HasMSA]>;
def SRLI_D : SRLI_D_ENC, SRLI_D_DESC, Requires<[HasMSA]>;
+def SRLR_B : SRLR_B_ENC, SRLR_B_DESC, Requires<[HasMSA]>;
+def SRLR_H : SRLR_H_ENC, SRLR_H_DESC, Requires<[HasMSA]>;
+def SRLR_W : SRLR_W_ENC, SRLR_W_DESC, Requires<[HasMSA]>;
+def SRLR_D : SRLR_D_ENC, SRLR_D_DESC, Requires<[HasMSA]>;
+
+def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC, Requires<[HasMSA]>;
+def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC, Requires<[HasMSA]>;
+def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC, Requires<[HasMSA]>;
+def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC, Requires<[HasMSA]>;
+
def ST_B: ST_B_ENC, ST_B_DESC, Requires<[HasMSA]>;
def ST_H: ST_H_ENC, ST_H_DESC, Requires<[HasMSA]>;
def ST_W: ST_W_ENC, ST_W_DESC, Requires<[HasMSA]>;
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll?rev=189467&r1=189466&r2=189467&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll Wed Aug 28 05:12:09 2013
@@ -42,6 +42,82 @@ declare <2 x i64> @llvm.mips.fclass.d(<2
; CHECK: st.d
; CHECK: .size llvm_mips_fclass_d_test
;
+ at llvm_mips_ftrunc_s_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
+ at llvm_mips_ftrunc_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_ftrunc_s_w_test() nounwind {
+entry:
+ %0 = load <4 x float>* @llvm_mips_ftrunc_s_w_ARG1
+ %1 = tail call <4 x i32> @llvm.mips.ftrunc.s.w(<4 x float> %0)
+ store <4 x i32> %1, <4 x i32>* @llvm_mips_ftrunc_s_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.ftrunc.s.w(<4 x float>) nounwind
+
+; CHECK: llvm_mips_ftrunc_s_w_test:
+; CHECK: ld.w
+; CHECK: ftrunc_s.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_ftrunc_s_w_test
+;
+ at llvm_mips_ftrunc_s_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
+ at llvm_mips_ftrunc_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_ftrunc_s_d_test() nounwind {
+entry:
+ %0 = load <2 x double>* @llvm_mips_ftrunc_s_d_ARG1
+ %1 = tail call <2 x i64> @llvm.mips.ftrunc.s.d(<2 x double> %0)
+ store <2 x i64> %1, <2 x i64>* @llvm_mips_ftrunc_s_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.ftrunc.s.d(<2 x double>) nounwind
+
+; CHECK: llvm_mips_ftrunc_s_d_test:
+; CHECK: ld.d
+; CHECK: ftrunc_s.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_ftrunc_s_d_test
+;
+ at llvm_mips_ftrunc_u_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
+ at llvm_mips_ftrunc_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_ftrunc_u_w_test() nounwind {
+entry:
+ %0 = load <4 x float>* @llvm_mips_ftrunc_u_w_ARG1
+ %1 = tail call <4 x i32> @llvm.mips.ftrunc.u.w(<4 x float> %0)
+ store <4 x i32> %1, <4 x i32>* @llvm_mips_ftrunc_u_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.ftrunc.u.w(<4 x float>) nounwind
+
+; CHECK: llvm_mips_ftrunc_u_w_test:
+; CHECK: ld.w
+; CHECK: ftrunc_u.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_ftrunc_u_w_test
+;
+ at llvm_mips_ftrunc_u_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
+ at llvm_mips_ftrunc_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_ftrunc_u_d_test() nounwind {
+entry:
+ %0 = load <2 x double>* @llvm_mips_ftrunc_u_d_ARG1
+ %1 = tail call <2 x i64> @llvm.mips.ftrunc.u.d(<2 x double> %0)
+ store <2 x i64> %1, <2 x i64>* @llvm_mips_ftrunc_u_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.ftrunc.u.d(<2 x double>) nounwind
+
+; CHECK: llvm_mips_ftrunc_u_d_test:
+; CHECK: ld.d
+; CHECK: ftrunc_u.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_ftrunc_u_d_test
+;
@llvm_mips_ftint_s_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_ftint_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll?rev=189467&r1=189466&r2=189467&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll Wed Aug 28 05:12:09 2013
@@ -267,6 +267,94 @@ declare <2 x i64> @llvm.mips.sra.d(<2 x
; CHECK: st.d
; CHECK: .size llvm_mips_sra_d_test
;
+ at llvm_mips_srar_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
+ at llvm_mips_srar_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
+ at llvm_mips_srar_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
+
+define void @llvm_mips_srar_b_test() nounwind {
+entry:
+ %0 = load <16 x i8>* @llvm_mips_srar_b_ARG1
+ %1 = load <16 x i8>* @llvm_mips_srar_b_ARG2
+ %2 = tail call <16 x i8> @llvm.mips.srar.b(<16 x i8> %0, <16 x i8> %1)
+ store <16 x i8> %2, <16 x i8>* @llvm_mips_srar_b_RES
+ ret void
+}
+
+declare <16 x i8> @llvm.mips.srar.b(<16 x i8>, <16 x i8>) nounwind
+
+; CHECK: llvm_mips_srar_b_test:
+; CHECK: ld.b
+; CHECK: ld.b
+; CHECK: srar.b
+; CHECK: st.b
+; CHECK: .size llvm_mips_srar_b_test
+;
+ at llvm_mips_srar_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
+ at llvm_mips_srar_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
+ at llvm_mips_srar_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
+
+define void @llvm_mips_srar_h_test() nounwind {
+entry:
+ %0 = load <8 x i16>* @llvm_mips_srar_h_ARG1
+ %1 = load <8 x i16>* @llvm_mips_srar_h_ARG2
+ %2 = tail call <8 x i16> @llvm.mips.srar.h(<8 x i16> %0, <8 x i16> %1)
+ store <8 x i16> %2, <8 x i16>* @llvm_mips_srar_h_RES
+ ret void
+}
+
+declare <8 x i16> @llvm.mips.srar.h(<8 x i16>, <8 x i16>) nounwind
+
+; CHECK: llvm_mips_srar_h_test:
+; CHECK: ld.h
+; CHECK: ld.h
+; CHECK: srar.h
+; CHECK: st.h
+; CHECK: .size llvm_mips_srar_h_test
+;
+ at llvm_mips_srar_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
+ at llvm_mips_srar_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
+ at llvm_mips_srar_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_srar_w_test() nounwind {
+entry:
+ %0 = load <4 x i32>* @llvm_mips_srar_w_ARG1
+ %1 = load <4 x i32>* @llvm_mips_srar_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.srar.w(<4 x i32> %0, <4 x i32> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_srar_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.srar.w(<4 x i32>, <4 x i32>) nounwind
+
+; CHECK: llvm_mips_srar_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: srar.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_srar_w_test
+;
+ at llvm_mips_srar_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
+ at llvm_mips_srar_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
+ at llvm_mips_srar_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_srar_d_test() nounwind {
+entry:
+ %0 = load <2 x i64>* @llvm_mips_srar_d_ARG1
+ %1 = load <2 x i64>* @llvm_mips_srar_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.srar.d(<2 x i64> %0, <2 x i64> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_srar_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.srar.d(<2 x i64>, <2 x i64>) nounwind
+
+; CHECK: llvm_mips_srar_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: srar.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_srar_d_test
+;
@llvm_mips_srl_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_srl_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
@llvm_mips_srl_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
@@ -355,6 +443,94 @@ declare <2 x i64> @llvm.mips.srl.d(<2 x
; CHECK: st.d
; CHECK: .size llvm_mips_srl_d_test
;
+ at llvm_mips_srlr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
+ at llvm_mips_srlr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
+ at llvm_mips_srlr_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
+
+define void @llvm_mips_srlr_b_test() nounwind {
+entry:
+ %0 = load <16 x i8>* @llvm_mips_srlr_b_ARG1
+ %1 = load <16 x i8>* @llvm_mips_srlr_b_ARG2
+ %2 = tail call <16 x i8> @llvm.mips.srlr.b(<16 x i8> %0, <16 x i8> %1)
+ store <16 x i8> %2, <16 x i8>* @llvm_mips_srlr_b_RES
+ ret void
+}
+
+declare <16 x i8> @llvm.mips.srlr.b(<16 x i8>, <16 x i8>) nounwind
+
+; CHECK: llvm_mips_srlr_b_test:
+; CHECK: ld.b
+; CHECK: ld.b
+; CHECK: srlr.b
+; CHECK: st.b
+; CHECK: .size llvm_mips_srlr_b_test
+;
+ at llvm_mips_srlr_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
+ at llvm_mips_srlr_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
+ at llvm_mips_srlr_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
+
+define void @llvm_mips_srlr_h_test() nounwind {
+entry:
+ %0 = load <8 x i16>* @llvm_mips_srlr_h_ARG1
+ %1 = load <8 x i16>* @llvm_mips_srlr_h_ARG2
+ %2 = tail call <8 x i16> @llvm.mips.srlr.h(<8 x i16> %0, <8 x i16> %1)
+ store <8 x i16> %2, <8 x i16>* @llvm_mips_srlr_h_RES
+ ret void
+}
+
+declare <8 x i16> @llvm.mips.srlr.h(<8 x i16>, <8 x i16>) nounwind
+
+; CHECK: llvm_mips_srlr_h_test:
+; CHECK: ld.h
+; CHECK: ld.h
+; CHECK: srlr.h
+; CHECK: st.h
+; CHECK: .size llvm_mips_srlr_h_test
+;
+ at llvm_mips_srlr_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
+ at llvm_mips_srlr_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
+ at llvm_mips_srlr_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_srlr_w_test() nounwind {
+entry:
+ %0 = load <4 x i32>* @llvm_mips_srlr_w_ARG1
+ %1 = load <4 x i32>* @llvm_mips_srlr_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.srlr.w(<4 x i32> %0, <4 x i32> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_srlr_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.srlr.w(<4 x i32>, <4 x i32>) nounwind
+
+; CHECK: llvm_mips_srlr_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: srlr.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_srlr_w_test
+;
+ at llvm_mips_srlr_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
+ at llvm_mips_srlr_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
+ at llvm_mips_srlr_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_srlr_d_test() nounwind {
+entry:
+ %0 = load <2 x i64>* @llvm_mips_srlr_d_ARG1
+ %1 = load <2 x i64>* @llvm_mips_srlr_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.srlr.d(<2 x i64> %0, <2 x i64> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_srlr_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.srlr.d(<2 x i64>, <2 x i64>) nounwind
+
+; CHECK: llvm_mips_srlr_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: srlr.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_srlr_d_test
+;
@llvm_mips_subs_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_subs_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
@llvm_mips_subs_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll?rev=189467&r1=189466&r2=189467&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll Wed Aug 28 05:12:09 2013
@@ -3,6 +3,50 @@
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
+ at llvm_mips_fcaf_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
+ at llvm_mips_fcaf_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
+ at llvm_mips_fcaf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_fcaf_w_test() nounwind {
+entry:
+ %0 = load <4 x float>* @llvm_mips_fcaf_w_ARG1
+ %1 = load <4 x float>* @llvm_mips_fcaf_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.fcaf.w(<4 x float> %0, <4 x float> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_fcaf_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.fcaf.w(<4 x float>, <4 x float>) nounwind
+
+; CHECK: llvm_mips_fcaf_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: fcaf.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_fcaf_w_test
+;
+ at llvm_mips_fcaf_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
+ at llvm_mips_fcaf_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
+ at llvm_mips_fcaf_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_fcaf_d_test() nounwind {
+entry:
+ %0 = load <2 x double>* @llvm_mips_fcaf_d_ARG1
+ %1 = load <2 x double>* @llvm_mips_fcaf_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.fcaf.d(<2 x double> %0, <2 x double> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_fcaf_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.fcaf.d(<2 x double>, <2 x double>) nounwind
+
+; CHECK: llvm_mips_fcaf_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: fcaf.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_fcaf_d_test
+;
@llvm_mips_fceq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fceq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
@llvm_mips_fceq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
@@ -135,6 +179,50 @@ declare <2 x i64> @llvm.mips.fclt.d(<2 x
; CHECK: st.d
; CHECK: .size llvm_mips_fclt_d_test
;
+ at llvm_mips_fcor_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
+ at llvm_mips_fcor_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
+ at llvm_mips_fcor_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_fcor_w_test() nounwind {
+entry:
+ %0 = load <4 x float>* @llvm_mips_fcor_w_ARG1
+ %1 = load <4 x float>* @llvm_mips_fcor_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.fcor.w(<4 x float> %0, <4 x float> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_fcor_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.fcor.w(<4 x float>, <4 x float>) nounwind
+
+; CHECK: llvm_mips_fcor_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: fcor.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_fcor_w_test
+;
+ at llvm_mips_fcor_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
+ at llvm_mips_fcor_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
+ at llvm_mips_fcor_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_fcor_d_test() nounwind {
+entry:
+ %0 = load <2 x double>* @llvm_mips_fcor_d_ARG1
+ %1 = load <2 x double>* @llvm_mips_fcor_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.fcor.d(<2 x double> %0, <2 x double> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_fcor_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.fcor.d(<2 x double>, <2 x double>) nounwind
+
+; CHECK: llvm_mips_fcor_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: fcor.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_fcor_d_test
+;
@llvm_mips_fcne_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fcne_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
@llvm_mips_fcne_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
@@ -179,6 +267,138 @@ declare <2 x i64> @llvm.mips.fcne.d(<2 x
; CHECK: st.d
; CHECK: .size llvm_mips_fcne_d_test
;
+ at llvm_mips_fcueq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
+ at llvm_mips_fcueq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
+ at llvm_mips_fcueq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_fcueq_w_test() nounwind {
+entry:
+ %0 = load <4 x float>* @llvm_mips_fcueq_w_ARG1
+ %1 = load <4 x float>* @llvm_mips_fcueq_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.fcueq.w(<4 x float> %0, <4 x float> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_fcueq_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.fcueq.w(<4 x float>, <4 x float>) nounwind
+
+; CHECK: llvm_mips_fcueq_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: fcueq.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_fcueq_w_test
+;
+ at llvm_mips_fcueq_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
+ at llvm_mips_fcueq_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
+ at llvm_mips_fcueq_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_fcueq_d_test() nounwind {
+entry:
+ %0 = load <2 x double>* @llvm_mips_fcueq_d_ARG1
+ %1 = load <2 x double>* @llvm_mips_fcueq_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.fcueq.d(<2 x double> %0, <2 x double> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_fcueq_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.fcueq.d(<2 x double>, <2 x double>) nounwind
+
+; CHECK: llvm_mips_fcueq_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: fcueq.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_fcueq_d_test
+;
+ at llvm_mips_fcult_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
+ at llvm_mips_fcult_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
+ at llvm_mips_fcult_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_fcult_w_test() nounwind {
+entry:
+ %0 = load <4 x float>* @llvm_mips_fcult_w_ARG1
+ %1 = load <4 x float>* @llvm_mips_fcult_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.fcult.w(<4 x float> %0, <4 x float> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_fcult_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.fcult.w(<4 x float>, <4 x float>) nounwind
+
+; CHECK: llvm_mips_fcult_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: fcult.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_fcult_w_test
+;
+ at llvm_mips_fcult_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
+ at llvm_mips_fcult_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
+ at llvm_mips_fcult_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_fcult_d_test() nounwind {
+entry:
+ %0 = load <2 x double>* @llvm_mips_fcult_d_ARG1
+ %1 = load <2 x double>* @llvm_mips_fcult_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.fcult.d(<2 x double> %0, <2 x double> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_fcult_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.fcult.d(<2 x double>, <2 x double>) nounwind
+
+; CHECK: llvm_mips_fcult_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: fcult.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_fcult_d_test
+;
+ at llvm_mips_fcule_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
+ at llvm_mips_fcule_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
+ at llvm_mips_fcule_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_fcule_w_test() nounwind {
+entry:
+ %0 = load <4 x float>* @llvm_mips_fcule_w_ARG1
+ %1 = load <4 x float>* @llvm_mips_fcule_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.fcule.w(<4 x float> %0, <4 x float> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_fcule_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.fcule.w(<4 x float>, <4 x float>) nounwind
+
+; CHECK: llvm_mips_fcule_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: fcule.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_fcule_w_test
+;
+ at llvm_mips_fcule_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
+ at llvm_mips_fcule_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
+ at llvm_mips_fcule_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_fcule_d_test() nounwind {
+entry:
+ %0 = load <2 x double>* @llvm_mips_fcule_d_ARG1
+ %1 = load <2 x double>* @llvm_mips_fcule_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.fcule.d(<2 x double> %0, <2 x double> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_fcule_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.fcule.d(<2 x double>, <2 x double>) nounwind
+
+; CHECK: llvm_mips_fcule_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: fcule.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_fcule_d_test
+;
@llvm_mips_fcun_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fcun_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
@llvm_mips_fcun_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
@@ -223,6 +443,94 @@ declare <2 x i64> @llvm.mips.fcun.d(<2 x
; CHECK: st.d
; CHECK: .size llvm_mips_fcun_d_test
;
+ at llvm_mips_fcune_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
+ at llvm_mips_fcune_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
+ at llvm_mips_fcune_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_fcune_w_test() nounwind {
+entry:
+ %0 = load <4 x float>* @llvm_mips_fcune_w_ARG1
+ %1 = load <4 x float>* @llvm_mips_fcune_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.fcune.w(<4 x float> %0, <4 x float> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_fcune_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.fcune.w(<4 x float>, <4 x float>) nounwind
+
+; CHECK: llvm_mips_fcune_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: fcune.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_fcune_w_test
+;
+ at llvm_mips_fcune_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
+ at llvm_mips_fcune_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
+ at llvm_mips_fcune_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_fcune_d_test() nounwind {
+entry:
+ %0 = load <2 x double>* @llvm_mips_fcune_d_ARG1
+ %1 = load <2 x double>* @llvm_mips_fcune_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.fcune.d(<2 x double> %0, <2 x double> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_fcune_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.fcune.d(<2 x double>, <2 x double>) nounwind
+
+; CHECK: llvm_mips_fcune_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: fcune.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_fcune_d_test
+;
+ at llvm_mips_fsaf_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
+ at llvm_mips_fsaf_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
+ at llvm_mips_fsaf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_fsaf_w_test() nounwind {
+entry:
+ %0 = load <4 x float>* @llvm_mips_fsaf_w_ARG1
+ %1 = load <4 x float>* @llvm_mips_fsaf_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.fsaf.w(<4 x float> %0, <4 x float> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_fsaf_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.fsaf.w(<4 x float>, <4 x float>) nounwind
+
+; CHECK: llvm_mips_fsaf_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: fsaf.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_fsaf_w_test
+;
+ at llvm_mips_fsaf_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
+ at llvm_mips_fsaf_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
+ at llvm_mips_fsaf_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_fsaf_d_test() nounwind {
+entry:
+ %0 = load <2 x double>* @llvm_mips_fsaf_d_ARG1
+ %1 = load <2 x double>* @llvm_mips_fsaf_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.fsaf.d(<2 x double> %0, <2 x double> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_fsaf_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.fsaf.d(<2 x double>, <2 x double>) nounwind
+
+; CHECK: llvm_mips_fsaf_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: fsaf.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_fsaf_d_test
+;
@llvm_mips_fseq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fseq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
@llvm_mips_fseq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
@@ -355,6 +663,50 @@ declare <2 x i64> @llvm.mips.fslt.d(<2 x
; CHECK: st.d
; CHECK: .size llvm_mips_fslt_d_test
;
+ at llvm_mips_fsor_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
+ at llvm_mips_fsor_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
+ at llvm_mips_fsor_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_fsor_w_test() nounwind {
+entry:
+ %0 = load <4 x float>* @llvm_mips_fsor_w_ARG1
+ %1 = load <4 x float>* @llvm_mips_fsor_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.fsor.w(<4 x float> %0, <4 x float> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_fsor_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.fsor.w(<4 x float>, <4 x float>) nounwind
+
+; CHECK: llvm_mips_fsor_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: fsor.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_fsor_w_test
+;
+ at llvm_mips_fsor_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
+ at llvm_mips_fsor_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
+ at llvm_mips_fsor_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_fsor_d_test() nounwind {
+entry:
+ %0 = load <2 x double>* @llvm_mips_fsor_d_ARG1
+ %1 = load <2 x double>* @llvm_mips_fsor_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.fsor.d(<2 x double> %0, <2 x double> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_fsor_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.fsor.d(<2 x double>, <2 x double>) nounwind
+
+; CHECK: llvm_mips_fsor_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: fsor.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_fsor_d_test
+;
@llvm_mips_fsne_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fsne_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
@llvm_mips_fsne_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
@@ -399,3 +751,223 @@ declare <2 x i64> @llvm.mips.fsne.d(<2 x
; CHECK: st.d
; CHECK: .size llvm_mips_fsne_d_test
;
+ at llvm_mips_fsueq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
+ at llvm_mips_fsueq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
+ at llvm_mips_fsueq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_fsueq_w_test() nounwind {
+entry:
+ %0 = load <4 x float>* @llvm_mips_fsueq_w_ARG1
+ %1 = load <4 x float>* @llvm_mips_fsueq_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.fsueq.w(<4 x float> %0, <4 x float> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_fsueq_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.fsueq.w(<4 x float>, <4 x float>) nounwind
+
+; CHECK: llvm_mips_fsueq_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: fsueq.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_fsueq_w_test
+;
+ at llvm_mips_fsueq_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
+ at llvm_mips_fsueq_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
+ at llvm_mips_fsueq_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_fsueq_d_test() nounwind {
+entry:
+ %0 = load <2 x double>* @llvm_mips_fsueq_d_ARG1
+ %1 = load <2 x double>* @llvm_mips_fsueq_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.fsueq.d(<2 x double> %0, <2 x double> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_fsueq_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.fsueq.d(<2 x double>, <2 x double>) nounwind
+
+; CHECK: llvm_mips_fsueq_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: fsueq.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_fsueq_d_test
+;
+ at llvm_mips_fsult_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
+ at llvm_mips_fsult_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
+ at llvm_mips_fsult_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_fsult_w_test() nounwind {
+entry:
+ %0 = load <4 x float>* @llvm_mips_fsult_w_ARG1
+ %1 = load <4 x float>* @llvm_mips_fsult_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.fsult.w(<4 x float> %0, <4 x float> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_fsult_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.fsult.w(<4 x float>, <4 x float>) nounwind
+
+; CHECK: llvm_mips_fsult_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: fsult.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_fsult_w_test
+;
+ at llvm_mips_fsult_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
+ at llvm_mips_fsult_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
+ at llvm_mips_fsult_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_fsult_d_test() nounwind {
+entry:
+ %0 = load <2 x double>* @llvm_mips_fsult_d_ARG1
+ %1 = load <2 x double>* @llvm_mips_fsult_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.fsult.d(<2 x double> %0, <2 x double> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_fsult_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.fsult.d(<2 x double>, <2 x double>) nounwind
+
+; CHECK: llvm_mips_fsult_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: fsult.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_fsult_d_test
+;
+ at llvm_mips_fsule_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
+ at llvm_mips_fsule_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
+ at llvm_mips_fsule_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_fsule_w_test() nounwind {
+entry:
+ %0 = load <4 x float>* @llvm_mips_fsule_w_ARG1
+ %1 = load <4 x float>* @llvm_mips_fsule_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.fsule.w(<4 x float> %0, <4 x float> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_fsule_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.fsule.w(<4 x float>, <4 x float>) nounwind
+
+; CHECK: llvm_mips_fsule_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: fsule.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_fsule_w_test
+;
+ at llvm_mips_fsule_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
+ at llvm_mips_fsule_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
+ at llvm_mips_fsule_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_fsule_d_test() nounwind {
+entry:
+ %0 = load <2 x double>* @llvm_mips_fsule_d_ARG1
+ %1 = load <2 x double>* @llvm_mips_fsule_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.fsule.d(<2 x double> %0, <2 x double> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_fsule_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.fsule.d(<2 x double>, <2 x double>) nounwind
+
+; CHECK: llvm_mips_fsule_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: fsule.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_fsule_d_test
+;
+ at llvm_mips_fsun_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
+ at llvm_mips_fsun_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
+ at llvm_mips_fsun_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_fsun_w_test() nounwind {
+entry:
+ %0 = load <4 x float>* @llvm_mips_fsun_w_ARG1
+ %1 = load <4 x float>* @llvm_mips_fsun_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.fsun.w(<4 x float> %0, <4 x float> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_fsun_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.fsun.w(<4 x float>, <4 x float>) nounwind
+
+; CHECK: llvm_mips_fsun_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: fsun.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_fsun_w_test
+;
+ at llvm_mips_fsun_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
+ at llvm_mips_fsun_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
+ at llvm_mips_fsun_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_fsun_d_test() nounwind {
+entry:
+ %0 = load <2 x double>* @llvm_mips_fsun_d_ARG1
+ %1 = load <2 x double>* @llvm_mips_fsun_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.fsun.d(<2 x double> %0, <2 x double> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_fsun_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.fsun.d(<2 x double>, <2 x double>) nounwind
+
+; CHECK: llvm_mips_fsun_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: fsun.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_fsun_d_test
+;
+ at llvm_mips_fsune_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
+ at llvm_mips_fsune_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
+ at llvm_mips_fsune_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_fsune_w_test() nounwind {
+entry:
+ %0 = load <4 x float>* @llvm_mips_fsune_w_ARG1
+ %1 = load <4 x float>* @llvm_mips_fsune_w_ARG2
+ %2 = tail call <4 x i32> @llvm.mips.fsune.w(<4 x float> %0, <4 x float> %1)
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_fsune_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.fsune.w(<4 x float>, <4 x float>) nounwind
+
+; CHECK: llvm_mips_fsune_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: fsune.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_fsune_w_test
+;
+ at llvm_mips_fsune_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
+ at llvm_mips_fsune_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
+ at llvm_mips_fsune_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_fsune_d_test() nounwind {
+entry:
+ %0 = load <2 x double>* @llvm_mips_fsune_d_ARG1
+ %1 = load <2 x double>* @llvm_mips_fsune_d_ARG2
+ %2 = tail call <2 x i64> @llvm.mips.fsune.d(<2 x double> %0, <2 x double> %1)
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_fsune_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.fsune.d(<2 x double>, <2 x double>) nounwind
+
+; CHECK: llvm_mips_fsune_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: fsune.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_fsune_d_test
+;
Modified: llvm/trunk/test/CodeGen/Mips/msa/bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/bit.ll?rev=189467&r1=189466&r2=189467&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/bit.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/bit.ll Wed Aug 28 05:12:09 2013
@@ -306,6 +306,82 @@ declare <2 x i64> @llvm.mips.srai.d(<2 x
; CHECK: st.d
; CHECK: .size llvm_mips_srai_d_test
;
+ at llvm_mips_srari_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
+ at llvm_mips_srari_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
+
+define void @llvm_mips_srari_b_test() nounwind {
+entry:
+ %0 = load <16 x i8>* @llvm_mips_srari_b_ARG1
+ %1 = tail call <16 x i8> @llvm.mips.srari.b(<16 x i8> %0, i32 7)
+ store <16 x i8> %1, <16 x i8>* @llvm_mips_srari_b_RES
+ ret void
+}
+
+declare <16 x i8> @llvm.mips.srari.b(<16 x i8>, i32) nounwind
+
+; CHECK: llvm_mips_srari_b_test:
+; CHECK: ld.b
+; CHECK: srari.b
+; CHECK: st.b
+; CHECK: .size llvm_mips_srari_b_test
+;
+ at llvm_mips_srari_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
+ at llvm_mips_srari_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
+
+define void @llvm_mips_srari_h_test() nounwind {
+entry:
+ %0 = load <8 x i16>* @llvm_mips_srari_h_ARG1
+ %1 = tail call <8 x i16> @llvm.mips.srari.h(<8 x i16> %0, i32 7)
+ store <8 x i16> %1, <8 x i16>* @llvm_mips_srari_h_RES
+ ret void
+}
+
+declare <8 x i16> @llvm.mips.srari.h(<8 x i16>, i32) nounwind
+
+; CHECK: llvm_mips_srari_h_test:
+; CHECK: ld.h
+; CHECK: srari.h
+; CHECK: st.h
+; CHECK: .size llvm_mips_srari_h_test
+;
+ at llvm_mips_srari_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
+ at llvm_mips_srari_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_srari_w_test() nounwind {
+entry:
+ %0 = load <4 x i32>* @llvm_mips_srari_w_ARG1
+ %1 = tail call <4 x i32> @llvm.mips.srari.w(<4 x i32> %0, i32 7)
+ store <4 x i32> %1, <4 x i32>* @llvm_mips_srari_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.srari.w(<4 x i32>, i32) nounwind
+
+; CHECK: llvm_mips_srari_w_test:
+; CHECK: ld.w
+; CHECK: srari.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_srari_w_test
+;
+ at llvm_mips_srari_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
+ at llvm_mips_srari_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_srari_d_test() nounwind {
+entry:
+ %0 = load <2 x i64>* @llvm_mips_srari_d_ARG1
+ %1 = tail call <2 x i64> @llvm.mips.srari.d(<2 x i64> %0, i32 7)
+ store <2 x i64> %1, <2 x i64>* @llvm_mips_srari_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.srari.d(<2 x i64>, i32) nounwind
+
+; CHECK: llvm_mips_srari_d_test:
+; CHECK: ld.d
+; CHECK: srari.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_srari_d_test
+;
@llvm_mips_srli_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_srli_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
@@ -382,3 +458,79 @@ declare <2 x i64> @llvm.mips.srli.d(<2 x
; CHECK: st.d
; CHECK: .size llvm_mips_srli_d_test
;
+ at llvm_mips_srlri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
+ at llvm_mips_srlri_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
+
+define void @llvm_mips_srlri_b_test() nounwind {
+entry:
+ %0 = load <16 x i8>* @llvm_mips_srlri_b_ARG1
+ %1 = tail call <16 x i8> @llvm.mips.srlri.b(<16 x i8> %0, i32 7)
+ store <16 x i8> %1, <16 x i8>* @llvm_mips_srlri_b_RES
+ ret void
+}
+
+declare <16 x i8> @llvm.mips.srlri.b(<16 x i8>, i32) nounwind
+
+; CHECK: llvm_mips_srlri_b_test:
+; CHECK: ld.b
+; CHECK: srlri.b
+; CHECK: st.b
+; CHECK: .size llvm_mips_srlri_b_test
+;
+ at llvm_mips_srlri_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
+ at llvm_mips_srlri_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
+
+define void @llvm_mips_srlri_h_test() nounwind {
+entry:
+ %0 = load <8 x i16>* @llvm_mips_srlri_h_ARG1
+ %1 = tail call <8 x i16> @llvm.mips.srlri.h(<8 x i16> %0, i32 7)
+ store <8 x i16> %1, <8 x i16>* @llvm_mips_srlri_h_RES
+ ret void
+}
+
+declare <8 x i16> @llvm.mips.srlri.h(<8 x i16>, i32) nounwind
+
+; CHECK: llvm_mips_srlri_h_test:
+; CHECK: ld.h
+; CHECK: srlri.h
+; CHECK: st.h
+; CHECK: .size llvm_mips_srlri_h_test
+;
+ at llvm_mips_srlri_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
+ at llvm_mips_srlri_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_srlri_w_test() nounwind {
+entry:
+ %0 = load <4 x i32>* @llvm_mips_srlri_w_ARG1
+ %1 = tail call <4 x i32> @llvm.mips.srlri.w(<4 x i32> %0, i32 7)
+ store <4 x i32> %1, <4 x i32>* @llvm_mips_srlri_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.srlri.w(<4 x i32>, i32) nounwind
+
+; CHECK: llvm_mips_srlri_w_test:
+; CHECK: ld.w
+; CHECK: srlri.w
+; CHECK: st.w
+; CHECK: .size llvm_mips_srlri_w_test
+;
+ at llvm_mips_srlri_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
+ at llvm_mips_srlri_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_srlri_d_test() nounwind {
+entry:
+ %0 = load <2 x i64>* @llvm_mips_srlri_d_ARG1
+ %1 = tail call <2 x i64> @llvm.mips.srlri.d(<2 x i64> %0, i32 7)
+ store <2 x i64> %1, <2 x i64>* @llvm_mips_srlri_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.srlri.d(<2 x i64>, i32) nounwind
+
+; CHECK: llvm_mips_srlri_d_test:
+; CHECK: ld.d
+; CHECK: srlri.d
+; CHECK: st.d
+; CHECK: .size llvm_mips_srlri_d_test
+;
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