[Mesa-dev] PATCH: R600 + SI: Add support for lds atomic add

Tom Stellard tom at stellard.net
Thu Aug 22 08:36:03 PDT 2013


On Thu, Aug 22, 2013 at 10:03:56AM +0200, Michel Dänzer wrote:
> On Mit, 2013-08-21 at 11:30 -0700, Tom Stellard wrote:
> > 
> > The attached patches fix some LDS bugs on SI and add support for atomic
> > add for R600 and SI.
> > 
> > Please Review.
> 
> About patch 4:
> 
> > diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
> > index ecc4718..09d5f01 100644
> > --- a/lib/Target/R600/SIInstrInfo.td
> > +++ b/lib/Target/R600/SIInstrInfo.td
> > @@ -362,6 +362,18 @@ class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
> >    let vdst = 0;
> >  }
> >  
> > +class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc> : DS <
> > +  op,
> > +  (outs rc:$vdst),
> > +  (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, i8imm:$offset0,
> > +       i8imm:$offset1),
> > +  asm#" $gds, $vdst, $addr, $data0, $offset0, $offset1, [M0]",
> > +  []> {
> > +  let mayStore = 1;
> > +  let mayLoad = 1;
> > +  let data1 = 0;
> > +}
> > +
> 
> I recently noticed in the ISA documentation that DS instructions using a
> single address use a single 16 bit offset field instead of two 8 bit
> fields. I've been meaning to update the existing code for
> DS_READ/WRITE_B32 accordingly.
> 

I noticed that too, I can make that change.

> 
> > diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> > index 136f69c..31a5ad2 100644
> > --- a/lib/Target/R600/SIInstructions.td
> > +++ b/lib/Target/R600/SIInstructions.td
> > diff --git a/lib/Target/R600/SILowerControlFlow.cpp b/lib/Target/R600/SILowerControlFlow.cpp
> > index 09cf25b..a6c43bb 100644
> > --- a/lib/Target/R600/SILowerControlFlow.cpp
> > +++ b/lib/Target/R600/SILowerControlFlow.cpp
> > @@ -488,6 +488,7 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
> >            NeedWQM = true;
> >            // Fall through
> >          case AMDGPU::DS_WRITE_B32:
> > +        case AMDGPU::DS_ADD_U32_RTN:
> >            NeedM0 = true;
> >            break;
> 
> I guess at some point we might want to use an InstrFlag for checking for
> DS instructions.
> 
> 

I'll fix this too.

-Tom




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