[llvm] r188967 - ARM: R9 is not safe to use for tcGPR.

[Jim Grosbach]

Author: grosbach
Date: Wed Aug 21 19:14:24 2013
New Revision: 188967

URL: http://llvm.org/viewvc/llvm-project?rev=188967&view=rev
Log:
ARM: R9 is not safe to use for tcGPR.

Indirect tail-calls shouldn't use R9 for the branch destination, as
it's not reliably a call-clobbered register.

rdar://14793425

Added:
    llvm/trunk/test/CodeGen/Thumb2/tail-call-r9.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=188967&r1=188966&r2=188967&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Wed Aug 21 19:14:24 2013
@@ -251,7 +251,7 @@ def hGPR : RegisterClass<"ARM", [i32], 3
 // to the saved value before the tail call, which would clobber a call address.
 // Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of
 // this class and the preceding one(!)  This is what we want.
-def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R9, R12)> {
+def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
   let AltOrders = [(and tcGPR, tGPR)];
   let AltOrderSelect = [{
       return MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();

Added: llvm/trunk/test/CodeGen/Thumb2/tail-call-r9.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/tail-call-r9.ll?rev=188967&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/tail-call-r9.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb2/tail-call-r9.ll Wed Aug 21 19:14:24 2013
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 | FileCheck %s
+
+ at foo = common global void ()* null, align 4
+
+; Make sure in the presence of a tail call, r9 doesn't get used to hold
+; the destination address. It's callee-saved in AAPCS.
+define arm_aapcscc void @test(i32 %a) nounwind {
+; CHECK-LABEL: test:
+; CHECK-NOT bx r9
+  %tmp = load void ()** @foo, align 4
+  tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r12}"() nounwind
+  tail call arm_aapcscc void %tmp() nounwind
+  ret void
+}