[PATCH] [mips][msa] Split MSA128 regset into size-specific sets containing the same registers.

[Daniel Sanders]

This patch splits the MSA128 register class into element-size specific sets containing the same registers. This is necessary to implement spill/reload for MSA registers correctly.

In big-endian mode, vectors elements are stored in big-endian order but the elements themselves are stored in array order. For example the byte order for v8i16 is 1032547698BADCFE. This means that the implementation of TargetInstrInfo::storeRegToStackSlot must choose between multiple store instructions according to the EVT (or more precisely, the size of the elements). Unfortunately storeRegToStackSlot does not provide the EVT. However, we can use register classes (which are provided) as a proxy for the EVT. This patch lays the groundwork to do this.

This patch should not cause any regressions in the existing MSA support. My next patch will implement bitcasts of big and little-endian vectors which will be needed to test spill and reload. The patch after that will implement spill/reload for MSA registers.

Daniel Sanders
Leading Software Design Engineer, MIPS Processor IP
Imagination Technologies Limited
www.imgtec.com<http://www.imgtec.com/>

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