R600: Various improvements

[Tom Stellard]

On Mon, Aug 19, 2013 at 12:25:25PM -0700, Vincent Lejeune wrote:
> From 1ca92fb228b1a8f3aa17a173db2e13addb721f7b Mon Sep 17 00:00:00 2001
> From: Vincent Lejeune <vljn at ovi.com>
> Date: Fri, 12 Jul 2013 15:26:11 +0200
> Subject: [PATCH] R600: Use StructurizeCFGPass for non SI targets
> 
> StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of
                      allows us
> shader from shadertoy (which exhibits complex control flow constructs) to works
the shaders                                                              to work
> correctly with respect to CFG handling (and allow us to detect potential bug in
                                              alllows                      bugs
> other part of the backend).
        parts
> 
> We provide a cmd line argument to disable the pass for debug purpose.
> ---
>  lib/Target/R600/AMDGPU.td                 | 5 +++++
>  lib/Target/R600/AMDGPUSubtarget.cpp       | 5 +++++
>  lib/Target/R600/AMDGPUSubtarget.h         | 2 ++
>  lib/Target/R600/AMDGPUTargetMachine.cpp   | 5 ++++-
>  lib/Target/R600/R600EmitClauseMarkers.cpp | 1 +
>  lib/Target/R600/R600Packetizer.cpp        | 2 +-
>  6 files changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/Target/R600/AMDGPU.td b/lib/Target/R600/AMDGPU.td
> index 0048e25..a722f55 100644
> --- a/lib/Target/R600/AMDGPU.td
> +++ b/lib/Target/R600/AMDGPU.td
> @@ -21,6 +21,11 @@ def FeatureDumpCode : SubtargetFeature <"DumpCode",
>          "true",
>          "Dump MachineInstrs in the CodeEmitter">;
>  
> +def FeatureIRStructurizer : SubtargetFeature <"EnableIRStructurizer",
> +        "EnableIRStructurizer",
> +        "true",
> +        "Enable IR Structurizer">;
> +
>  // Target features
>  
>  def FeatureFP64     : SubtargetFeature<"fp64",
> diff --git a/lib/Target/R600/AMDGPUSubtarget.cpp b/lib/Target/R600/AMDGPUSubtarget.cpp
> index 8ed5a74..18099ac 100644
> --- a/lib/Target/R600/AMDGPUSubtarget.cpp
> +++ b/lib/Target/R600/AMDGPUSubtarget.cpp
> @@ -37,6 +37,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
>    Gen = AMDGPUSubtarget::R600;
>    FP64 = false;
>    CaymanISA = false;
> +  EnableIRStructurizer = false;
>    ParseSubtargetFeatures(GPU, FS);
>    DevName = GPU;
>  }
> @@ -66,6 +67,10 @@ AMDGPUSubtarget::hasCaymanISA() const {
>    return CaymanISA;
>  }
>  bool
> +AMDGPUSubtarget::IsIRStructurizerEnabled() const {
> +  return EnableIRStructurizer;
> +}
> +bool
>  AMDGPUSubtarget::isTargetELF() const {
>    return false;
>  }
> diff --git a/lib/Target/R600/AMDGPUSubtarget.h b/lib/Target/R600/AMDGPUSubtarget.h
> index 8c65096..29b7204 100644
> --- a/lib/Target/R600/AMDGPUSubtarget.h
> +++ b/lib/Target/R600/AMDGPUSubtarget.h
> @@ -48,6 +48,7 @@ private:
>    enum Generation Gen;
>    bool FP64;
>    bool CaymanISA;
> +  bool EnableIRStructurizer;
>  
>    InstrItineraryData InstrItins;
>  
> @@ -63,6 +64,7 @@ public:
>    enum Generation getGeneration() const;
>    bool hasHWFP64() const;
>    bool hasCaymanISA() const;
> +  bool IsIRStructurizerEnabled() const;
>  
>    // Helper functions to simplify if statements
>    bool isTargetELF() const;

Everything below this point seems unrelated.  Can you either remove it
our split it out int a separate patch.

-Tom
> diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp
> index 5ebc5f2..cf94710 100644
> --- a/lib/Target/R600/AMDGPUTargetMachine.cpp
> +++ b/lib/Target/R600/AMDGPUTargetMachine.cpp
> @@ -33,6 +33,7 @@
>  #include "llvm/Transforms/Scalar.h"
>  #include <llvm/CodeGen/Passes.h>
>  
> +
>  using namespace llvm;
>  
>  extern "C" void LLVMInitializeR600Target() {
> @@ -120,8 +121,10 @@ bool
>  AMDGPUPassConfig::addPreISel() {
>    const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
>    addPass(createFlattenCFGPass());
> -  if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
> +  if (ST.IsIRStructurizerEnabled() ||
> +      ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS)
>      addPass(createStructurizeCFGPass());
> +  if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
>      addPass(createSIAnnotateControlFlowPass());
>    } else {
>      addPass(createR600TextureIntrinsicsReplacer());
> diff --git a/lib/Target/R600/R600EmitClauseMarkers.cpp b/lib/Target/R600/R600EmitClauseMarkers.cpp
> index fac2b47..a055639 100644
> --- a/lib/Target/R600/R600EmitClauseMarkers.cpp
> +++ b/lib/Target/R600/R600EmitClauseMarkers.cpp
> @@ -84,6 +84,7 @@ private:
>      switch (MI->getOpcode()) {
>      case AMDGPU::KILL:
>      case AMDGPU::RETURN:
> +    case AMDGPU::IMPLICIT_DEF:
>        return true;
>      default:
>        return false;
> diff --git a/lib/Target/R600/R600Packetizer.cpp b/lib/Target/R600/R600Packetizer.cpp
> index 6c70052..1d5d96a 100644
> --- a/lib/Target/R600/R600Packetizer.cpp
> +++ b/lib/Target/R600/R600Packetizer.cpp
> @@ -336,7 +336,7 @@ bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
>      MachineBasicBlock::iterator End = MBB->end();
>      MachineBasicBlock::iterator MI = MBB->begin();
>      while (MI != End) {
> -      if (MI->isKill() ||
> +      if (MI->isKill() || MI->getOpcode() == AMDGPU::IMPLICIT_DEF ||
>            (MI->getOpcode() == AMDGPU::CF_ALU && !MI->getOperand(8).getImm())) {
>          MachineBasicBlock::iterator DeleteMI = MI;
>          ++MI;
> -- 
> 1.8.3.1
>