[PATCH] let tablegen compute maximum lanemask for a regs/regclasses

[Matthias Braun]

On Aug 13, 2013, at 4:32 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:

> 
> On Aug 13, 2013, at 3:58 PM, Matthias Braun <mbraun at apple.com> wrote:
> 
>> MatzeB added you to the CC list for the revision "let tablegen compute maximum lanemask for a regs/regclasses".
>> 
>> Let tablegen compute the combination of subregister lanemasks for all
>> subregisters in a register/register class. This is preparation for further
>> work subregister allocation
>> 
>> http://llvm-reviews.chandlerc.com/D1392
>> 
>> Files:
>> include/llvm/Target/TargetRegisterInfo.h
>> utils/TableGen/CodeGenRegisters.cpp
>> utils/TableGen/CodeGenRegisters.h
>> utils/TableGen/RegisterInfoEmitter.cpp
>> 
>> Index: include/llvm/Target/TargetRegisterInfo.h
>> ===================================================================
>> --- include/llvm/Target/TargetRegisterInfo.h
>> +++ include/llvm/Target/TargetRegisterInfo.h
>> @@ -45,6 +45,7 @@
>>  const vt_iterator VTs;
>>  const uint32_t *SubClassMask;
>>  const uint16_t *SuperRegIndices;
>> +  const unsigned LaneMask;
>>  const sc_iterator SuperClasses;
>>  ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
>> 
>> @@ -194,13 +195,21 @@
>>  ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
>>    return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
>>  }
>> +
>> +  /// return the combination of all lanemasks of register in this class.
>> +  /// The lanemasks of the registers are again the combination of all lanemasks
>> +  /// of their subregisters.
> 
> Nits: Capitalize returns, and ‘lane mask’ in two words.
> 
>> /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
>> /// registers. These are used by codegen, not by MC.
>> struct TargetRegisterInfoDesc {
>>  unsigned CostPerUse;          // Extra cost of instructions using register.
>>  bool inAllocatableClass;      // Register belongs to an allocatable regclass.
>> +  unsigned LaneMask;            // combination of all subregister lane masks
>> };
> 
> This is potentially very expensive - some targets have lots of registers. Do you actually need this?
Well at some points live ranges of physical registers are calculated, so having the maximum lane mask for a specific register will be required. Anyway it is easy to switch to an approach where they are lazily compute on the demand by the passes that need them and not being precomputed by tablegen.

> 
>> +  // compute lanemask combinations for register classes
>> +  for (size_t c = 0, ce = RegClasses.size(); c != ce; ++c) {
>> +    CodeGenRegisterClass *RegClass = RegClasses[c];
>> +    const CodeGenRegister::Set &Registers = RegClass->getMembers();
>> +    unsigned LaneMask = 0;
>> +    for (CodeGenRegister::Set::iterator R = Registers.begin(),
>> +         RE = Registers.end(); R != RE; ++R) {
>> +      LaneMask |= (*R)->LaneMask;
>> +    }
>> +    RegClass->LaneMask = LaneMask;
>> +  }
> 
> Can you use CodeGenRegisterClass::SubClassWithSubReg instead of computing this via the registers?
I wouldn’t get something computed for all register classes that way, would I?

> 
>> +    /// combination of the lanemasks of all subregisters
> 
> See http://llvm.org/docs/CodingStandards.html#commenting
> 
> "When writing comments, write them as English prose, which means they should use proper capitalization, punctuation, etc."
> 
> Thanks,
> /jakob
I will incorporate the other points into a new version.

Greetings,
	Matthias

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