[llvm] r188344 - [mips] Fix bug in parsing accumulator registers.

Akira Hatanaka ahatanaka at mips.com
Tue Aug 13 18:15:53 PDT 2013


Author: ahatanak
Date: Tue Aug 13 20:15:52 2013
New Revision: 188344

URL: http://llvm.org/viewvc/llvm-project?rev=188344&view=rev
Log:
[mips] Fix bug in parsing accumulator registers.


Modified:
    llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
    llvm/trunk/test/MC/Mips/mips-dsp-instructions.s

Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=188344&r1=188343&r2=188344&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Tue Aug 13 20:15:52 2013
@@ -861,8 +861,8 @@ int MipsAsmParser::matchFCCRegisterName(
 
 int MipsAsmParser::matchACRegisterName(StringRef Name) {
 
-  if (Name.startswith("acc")) {
-    StringRef NumString = Name.substr(3);
+  if (Name.startswith("ac")) {
+    StringRef NumString = Name.substr(2);
     unsigned IntVal;
     if (NumString.getAsInteger(10, IntVal))
       return -1; // This is not an integer.

Modified: llvm/trunk/test/MC/Mips/mips-dsp-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-dsp-instructions.s?rev=188344&r1=188343&r2=188344&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips-dsp-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/mips-dsp-instructions.s Tue Aug 13 20:15:52 2013
@@ -22,6 +22,13 @@
 # CHECK:   precr_sra_r.ph.w  $25, $26, 0     # encoding: [0x7f,0x59,0x07,0xd1]
 # CHECK:   precr_sra_r.ph.w  $25, $26, 31    # encoding: [0x7f,0x59,0xff,0xd1]
 
+# CHECK:    mult $ac3, $2, $3               # encoding: [0x00,0x43,0x18,0x18]
+# CHECK:    multu $ac2, $4, $5              # encoding: [0x00,0x85,0x10,0x19]
+# CHECK:    madd $ac1, $6, $7               # encoding: [0x70,0xc7,0x08,0x00]
+# CHECK:    maddu $ac0, $8, $9              # encoding: [0x71,0x09,0x00,0x01]
+# CHECK:    msub $ac3, $10, $11             # encoding: [0x71,0x4b,0x18,0x04]
+# CHECK:    msubu $ac2, $12, $13            # encoding: [0x71,0x8d,0x10,0x05]
+
   precrq.qb.ph    $16,$17,$18
   precrq.ph.w     $17,$18,$19
   precrq_rs.ph.w  $18,$19,$20
@@ -42,3 +49,10 @@
   precr_sra.ph.w  $24,$25,31
   precr_sra_r.ph.w  $25,$26,0
   precr_sra_r.ph.w  $25,$26,31
+
+  mult $ac3, $2, $3
+  multu $ac2, $4, $5
+  madd $ac1, $6, $7
+  maddu $ac0, $8, $9
+  msub $ac3, $10, $11
+  msubu $ac2, $12, $13





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